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Update verilator's emulator.cc SIM_FILE_REQS

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This commit is contained in:
Jerry Zhao
2023-04-17 16:20:52 -07:00
parent 8c47f50a73
commit c6bf50bc9d
2 changed files with 3 additions and 2 deletions
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2
generators/testchipip

Submodule generators/testchipip updated: efaa073f5b...e830ecf6ca

3
sims/verilator/Makefile
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@@ -60,7 +60,8 @@ SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc