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Merge remote-tracking branch 'origin/rebar-dev'

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Abraham Gonzalez
2019-05-28 14:21:57 -07:00
parent e0e1acdd57 767e59f382
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REBAR CI
========
Website: https://circleci.com/gh/ucb-bar/project-template
CircleCI Brief Explanation
---------------------------
CircleCI is controlled by the `config.yml` script.
It consists of a *workflow* which has a series of *jobs* within it that do particular tasks.
All jobs in the workflow must pass for the CI run to be successful.
At the bottom of the `config.yml` there is a `workflows:` section that specifies the order in which the jobs of the workflow should run.
For example:
- prepare-rocketchip:
requires:
- install-riscv-toolchain
- install-verilator
This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` and `install-verilator` steps to run before it can run.
All jobs in the CI workflow are specified at the top of `config.yml`
They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment.
Finally, in the `steps:` section, the steps are run sequentially and state persists throughout a job.
So when you run something like `checkout` the next step has the checked out code.
Caching in the job is done by giving a file to cache on.
`restore_cache:` loads the cache into the environment if the key matches while `save_cache:` writes to the cache with the key IF IT IS NOT PRESENT.
Note, if the cache is already present for that key, the write to it is ignored.
Here the key is built from a string where the `checksum` portion converts the file given into a hash.
.circleci directory
-------------------
This directory contains all the collateral for the REBAR CI to work.
The following is included:
build-toolchains.sh # build either riscv-tools or esp-tools
build-verilator.sh # build verilator
create-hash.sh # create hashes of riscv-tools/esp-tools so circleci caching can work
do-rtl-build.sh # use verilator to build a sim executable
config.yml # main circleci config script to enumerate jobs/workflows
How things are setup for REBAR
------------------------------
The steps for CI to run are as follows.
1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run).
The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused).
2nd, install verilator using the `*.mk` to cache unique versions of verilator (mainly for if verilator is bumped).
3rd, create the simulator binary.
This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary.
This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again).
4th, finally run the tests that were wanted.

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#!/bin/bash
# create the riscv tools/esp tools binaries
# passed in as <riscv-tools or esp-tools>
# turn echo on and error on earliest command
set -ex
if [ ! -d "$HOME/$1-install" ]; then
cd $HOME/
# init all submodules including the tools
REBAR_DIR=$HOME/project ./project/scripts/build-toolchains.sh $1
fi

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.circleci/build-verilator.sh Executable file
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#!/bin/bash
# build verilator
# turn echo on and error on earliest command
set -ex
cd $HOME/project
cd sims/verisim
if [ ! -d "$HOME/project/sims/verisim/verilator" ]; then
# make verilator
make verilator_install
fi

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# CircleCI Configuration File
# version of circleci
version: 2
# set of jobs to run
jobs:
install-riscv-toolchain:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- run:
name: Building riscv-tools toolchain
command: |
.circleci/build-toolchains.sh riscv-tools
no_output_timeout: 120m
- save_cache:
key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
paths:
- "/home/riscvuser/riscv-tools-install"
install-esp-toolchain:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
- run:
name: Building esp-tools toolchain
command: |
.circleci/build-toolchains.sh esp-tools
no_output_timeout: 120m
- save_cache:
key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
paths:
- "/home/riscvuser/esp-tools-install"
install-verilator:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Build Verilator
command: |
.circleci/build-verilator.sh
no_output_timeout: 120m
- save_cache:
key: verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
paths:
- "/home/riscvuser/project/sims/verisim/verilator"
prepare-example:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the example subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=example
no_output_timeout: 120m
- save_cache:
key: example-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-boomexample:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the boomexample subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig
no_output_timeout: 120m
- save_cache:
key: boomexample-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-boomrocketexample:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the boomrocketexample subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig
no_output_timeout: 120m
- save_cache:
key: boomrocketexample-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-boom:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the boom subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=boom
no_output_timeout: 120m
- save_cache:
key: boom-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-rocketchip:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the rocketchip subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip
no_output_timeout: 120m
- save_cache:
key: rocketchip-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
prepare-hwacha-verilog-only:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }}
- run:
name: Building the hwacha subproject using Verilator
command: .circleci/do-rtl-build.sh SUB_PROJECT=hwacha verilog
no_output_timeout: 120m
- save_cache:
key: hwacha-{{ .Branch }}-{{ .Revision }}
paths:
- "/home/riscvuser/project"
example-run-benchmark-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- example-{{ .Branch }}-{{ .Revision }}
- run:
name: Run example benchmark tests
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example
boomexample-run-benchmark-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- boomexample-{{ .Branch }}-{{ .Revision }}
- run:
name: Run boomexample benchmark tests
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig
boomrocketexample-run-benchmark-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- boomrocketexample-{{ .Branch }}-{{ .Revision }}
- run:
name: Run boomrocketexample benchmark tests
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig
boom-run-benchmark-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- boom-{{ .Branch }}-{{ .Revision }}
- run:
name: Run boom benchmark tests
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boom
rocketchip-run-benchmark-tests:
docker:
- image: riscvboom/riscvboom-images:0.0.5
environment:
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
TERM: dumb
steps:
# Checkout the code
- checkout
- run:
name: Create hash of toolchains
command: |
.circleci/create-hash.sh
- restore_cache:
keys:
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
- restore_cache:
keys:
- rocketchip-{{ .Branch }}-{{ .Revision }}
- run:
name: Run rocketchip benchmark tests
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=rocketchip
# hwacha-run-benchmark-tests:
# docker:
# - image: riscvboom/riscvboom-images:0.0.5
# environment:
# JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
# TERM: dumb
#
# steps:
# # Checkout the code
# - checkout
#
# - run:
# name: Create hash of toolchains
# command: |
# .circleci/create-hash.sh
#
# - restore_cache:
# keys:
# - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
#
# - restore_cache:
# keys:
# - hwacha-{{ .Branch }}-{{ .Revision }}
#
# - run:
# name: Run hwacha benchmark tests
# command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha
# Order and dependencies of jobs to run
workflows:
version: 2
build-and-test-rebar-integration:
jobs:
# Make the toolchains
- install-riscv-toolchain
- install-esp-toolchain
# Build verilator
- install-verilator
# Prepare the verilator builds
- prepare-example:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-boomexample:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-boomrocketexample:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-boom:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-rocketchip:
requires:
- install-riscv-toolchain
- install-verilator
- prepare-hwacha-verilog-only:
requires:
- install-riscv-toolchain # TODO: Remove when esp-tools is used
- install-esp-toolchain
- install-verilator
# Run the respective tests
# Run the example tests
- example-run-benchmark-tests:
requires:
- install-riscv-toolchain
- prepare-example
- boomexample-run-benchmark-tests:
requires:
- install-riscv-toolchain
- prepare-boomexample
- boomrocketexample-run-benchmark-tests:
requires:
- install-riscv-toolchain
- prepare-boomrocketexample
- boom-run-benchmark-tests:
requires:
- install-riscv-toolchain
- prepare-boom
- rocketchip-run-benchmark-tests:
requires:
- install-riscv-toolchain
- prepare-rocketchip
# - hwacha-run-benchmark-tests:
# requires:
# - install-riscv-toolchain # TODO: Remove when esp-tools is used
# - install-esp-toolchain
# - prepare-hwacha

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#!/bin/bash
# get the hash of riscv-tools
# turn echo on and error on earliest command
set -ex
# enter bhd repo
cd $HOME/project
# get the version of riscv-tools from the git submodule hash
git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash
git submodule status | grep "esp-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/esp-tools.hash
echo "Hashfile for riscv-tools and esp-tools created in $HOME"
echo "Contents: riscv-tools:$(cat $HOME/riscv-tools.hash)"
echo "Contents: esp-tools:$(cat $HOME/esp-tools.hash)"

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.circleci/do-rtl-build.sh Executable file
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#!/bin/bash
# create the different verilator builds
# argument is the make command string
# turn echo on and error on earliest command
set -ex
# init all submodules
cd $HOME/project
./scripts/init-submodules-no-riscv-tools.sh
# enter the verisim directory and build the specific config
cd sims/verisim
make clean
# run the particular build command
make JAVA_ARGS="-Xmx2G -Xss8M" $@
rm -rf ../../project

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.ctags Normal file
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--langdef=scala
--langmap=scala:.scala
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/
--regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/
--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/
--regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/

1
.ctagsignore Normal file
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*/target

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.gitignore vendored
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bootrom
bootrom/*
/Makefrag.pkgs
target
*.jar
*.stamp
/vsim
/verisim/generated-src*
/verisim/simulator-*
/verisim/verilator
simv*
*.vcd
*.swp
.idea
.DS_Store
tags

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.gitmodules vendored
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[submodule "rocket-chip"]
path = rocket-chip
path = generators/rocket-chip
url = https://github.com/ucb-bar/rocket-chip.git
[submodule "testchipip"]
path = testchipip
path = generators/testchipip
url = https://github.com/ucb-bar/testchipip.git
[submodule "barstools"]
path = barstools
path = tools/barstools
url = https://github.com/ucb-bar/barstools.git
[submodule "tools/chisel3"]
path = tools/chisel3
url = https://github.com/freechipsproject/chisel3.git
[submodule "tools/firrtl"]
path = tools/firrtl
url = https://github.com/freechipsproject/firrtl
[submodule "riscv-tools"]
path = toolchains/riscv-tools
url = https://github.com/riscv/riscv-tools.git
[submodule "esp-tools"]
path = toolchains/esp-tools
url = https://github.com/ucb-bar/esp-tools.git
[submodule "tools/torture"]
path = tools/torture
url = git@github.com:ucb-bar/riscv-torture.git
[submodule "generators/boom"]
path = generators/boom
url = git@github.com:riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"]
path = generators/sifive-blocks
url = git@github.com:sifive/sifive-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = git@github.com:ucb-bar/hwacha.git

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version: 2
formats: all
sphinx:
configuration: docs/conf.py
python:
install:
- requirements: docs/requirements.txt

111
Makefrag
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ROCKETCHIP_DIR=$(base_dir)/rocket-chip
TESTCHIP_DIR = $(base_dir)/testchipip
SCALA_VERSION=2.12.4
SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
PACKAGES=rocket-chip testchipip barstools
SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
mkdir -p $(dir $@)
cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
touch $@
build_dir=$(sim_dir)/generated-src
CHISEL_ARGS ?=
ifneq ($(PROJECT),example)
long_name=$(PROJECT).$(CONFIG)
else
long_name=$(PROJECT).$(MODEL).$(CONFIG)
endif
FIRRTL_FILE ?=$(build_dir)/$(long_name).fir
ANNO_FILE ?=$(build_dir)/$(long_name).anno.json
VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
TOP_FIR ?=$(build_dir)/$(long_name).top.fir
TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json
HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir
HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json
HARNESS_SMEMS_FILE ?=$(build_dir)/$(long_name).harness.mems.v
HARNESS_SMEMS_CONF ?=$(build_dir)/$(long_name).harness.mems.conf
HARNESS_SMEMS_FIR ?=$(build_dir)/$(long_name).harness.mems.fir
SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir
sim_dotf ?= $(build_dir)/sim_files.f
sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops
$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
HARNESS_MACROCOMPILER_MODE = --mode synflops
$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
regression-tests = \
rv64ud-v-fcvt \
rv64ud-p-fdiv \
rv64ud-v-fadd \
rv64uf-v-fadd \
rv64um-v-mul \
rv64mi-p-breakpoint \
rv64uc-v-rvc \
rv64ud-v-structural \
rv64si-p-wfi \
rv64um-v-divw \
rv64ua-v-lrsc \
rv64ui-v-fence_i \
rv64ud-v-fcvt_w \
rv64uf-v-fmin \
rv64ui-v-sb \
rv64ua-v-amomax_d \
rv64ud-v-move \
rv64ud-v-fclass \
rv64ua-v-amoand_d \
rv64ua-v-amoxor_d \
rv64si-p-sbreak \
rv64ud-v-fmadd \
rv64uf-v-ldst \
rv64um-v-mulh \
rv64si-p-dirty
output_dir=$(sim_dir)/output
$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
mkdir -p $(output_dir)
ln -sf $< $@

36
README.md
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@@ -1,4 +1,8 @@
# RISC-V Project Template
# RISC-V Project Template [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master)
**This branch is under development**
**It currently has many submodules**
**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodules to clone**
This is a starter template for your custom RISC-V project. It will allow you
to leverage the Chisel HDL and RocketChip SoC generator to produce a
@@ -46,6 +50,16 @@ build an alternate configuration.
make PROJECT=yourproject CONFIG=YourConfig
./simulator-yourproject-YourConfig ...
Additionally, you can use a helper make rule to run your simulation binary. The output will be in the "verisim"
directory under the file names: `<binary-name>.<type of project/config/etc it ran on>.*`
# first make your verisim rtl simulator binary
make SUB_PROJECT=example
# then run the binary (with no vcd generation)
make SUB_PROJECT=example BINARY=<my-riscv-binary> run-binary
# then run the binary (with vcd generation)
make SUB_PROJECT=example BINARY=<my-riscv-binary> run-binary-debug
## Submodules and Subdirectories
The submodules and subdirectories for the project template are organized as
@@ -58,6 +72,26 @@ follows.
* bootrom - sources for the first-stage bootloader included in the Boot ROM
* src/main/scala - scala source files for your project go here
## For submodule developers
Depending on the submodule that you develop in, you might want to run things out of the submodule.
For example, `boom` has its own Generator, package, top module, and configurations separate from
the `example` package in `src/main/scala`. Thus, to build a `boom` project you do something like
the following:
make SBT_PROJECT=boom PROJECT=boom.system CONFIG=<BOOM Config to use> TOP=ExampleBoomSystem
However, that is very long to write everytime there is a compile. Thus, a shorthand way to build
the subproject is the following:
make SUB_PROJECT=boom CONFIG=<BOOM Config to use>
This sets the proper configuration flags for make to work correctly.
Currently, the supported `SUB_PROJECT` flags are:
* boom - to build and run `boom` subproject configurations
## Using the block device
The default example project just provides the Rocket coreplex, memory, and

46
build.sbt
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@@ -8,21 +8,29 @@ lazy val commonSettings = Seq(
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
case _ => MergeStrategy.first}},
scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.1" % "test",
libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3",
libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test",
libraryDependencies += "org.json4s" %% "json4s-native" % "3.6.1",
libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
libraryDependencies += "edu.berkeley.cs" %% "firrtl-interpreter" % "1.2-SNAPSHOT",
libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.1",
libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0",
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases"),
Resolver.mavenLocal))
lazy val rocketchip = RootProject(file("rocket-chip"))
lazy val rebarFirrtl = (project in file("tools/firrtl"))
.settings(commonSettings)
lazy val testchipip = project.settings(commonSettings)
lazy val rocketchip = RootProject(file("generators/rocket-chip"))
lazy val rebarrocketchip = project
.dependsOn(rocketchip)
.settings(commonSettings)
lazy val testchipip = (project in file("generators/testchipip"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)
// Checks for -DROCKET_USE_MAVEN.
// If it's there, use a maven dependency.
@@ -36,16 +44,34 @@ def conditionalDependsOn(prj: Project): Project = {
prj.dependsOn(testchipip)
}
}
lazy val example = conditionalDependsOn(project in file("."))
lazy val example = conditionalDependsOn(project in file("generators/example"))
.dependsOn(boom, hwacha, sifive_blocks)
.settings(commonSettings)
lazy val tapeout = conditionalDependsOn(project in file("./barstools/tapeout/"))
lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
.settings(commonSettings)
lazy val mdf = (project in file("./barstools/mdf/scalalib/"))
lazy val hwacha = (project in file ("generators/hwacha"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)
lazy val `barstools-macros` = conditionalDependsOn(project in file("./barstools/macros/"))
lazy val boom = (project in file("generators/boom"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
.dependsOn(rebarFirrtl)
.settings(commonSettings)
lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
.settings(commonSettings)
lazy val `barstools-macros` = (project in file("./tools/barstools/macros/"))
.dependsOn(mdf, rebarrocketchip, rebarFirrtl)
.enablePlugins(sbtassembly.AssemblyPlugin)
.settings(commonSettings)
.dependsOn(mdf)
lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
.dependsOn(rebarrocketchip)
.settings(commonSettings)

135
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@@ -0,0 +1,135 @@
#########################################################################################
# set default shell for make
#########################################################################################
SHELL=/bin/bash
#########################################################################################
# variables to get all *.scala files
#########################################################################################
lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null)
PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks example
SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala))
#########################################################################################
# rocket and testchipip classes
#########################################################################################
ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
#########################################################################################
# jar creation variables and rules
#########################################################################################
FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
$(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala)
$(MAKE) -C $(REBAR_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(REBAR_FIRRTL_DIR) build-scala
mkdir -p $(dir $@)
cp -p $(REBAR_FIRRTL_DIR)/utils/bin/firrtl.jar $@
touch $@
#########################################################################################
# create simulation args file rule
#########################################################################################
$(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
#########################################################################################
# create firrtl file rule and variables
#########################################################################################
CHISEL_ARGS ?=
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
#########################################################################################
# create verilog files rules and variables
#########################################################################################
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops
$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
HARNESS_MACROCOMPILER_MODE = --mode synflops
$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
#########################################################################################
# helper rule to just make verilog files
#########################################################################################
.PHONY: verilog
verilog: $(sim_vsrcs)
#########################################################################################
# helper rules to run simulator
#########################################################################################
run-binary: $(sim)
$(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# run assembly/benchmarks rules
#########################################################################################
$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
mkdir -p $(output_dir)
ln -sf $< $@
$(output_dir)/%.run: $(output_dir)/% $(sim)
$(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@
$(output_dir)/%.out: $(output_dir)/% $(sim)
$(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@
#########################################################################################
# include build/project specific makefrags made from the generator
#########################################################################################
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d
endif
#########################################################################################
# default regression tests variables and rules
# TODO: Remove in favor of each project having its own regression tests?
#########################################################################################
regression-tests = \
rv64ud-v-fcvt \
rv64ud-p-fdiv \
rv64ud-v-fadd \
rv64uf-v-fadd \
rv64um-v-mul \
rv64mi-p-breakpoint \
rv64uc-v-rvc \
rv64ud-v-structural \
rv64si-p-wfi \
rv64um-v-divw \
rv64ua-v-lrsc \
rv64ui-v-fence_i \
rv64ud-v-fcvt_w \
rv64uf-v-fmin \
rv64ui-v-sb \
rv64ua-v-amomax_d \
rv64ud-v-move \
rv64ud-v-fclass \
rv64ua-v-amoand_d \
rv64ua-v-amoxor_d \
rv64si-p-sbreak \
rv64ud-v-fmadd \
rv64uf-v-ldst \
rv64um-v-mulh \
rv64si-p-dirty
.PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))

11
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@@ -0,0 +1,11 @@
Berkeley Out-of-Order Machine (BOOM)
==============================================
The `Berkeley Out-of-Order Machine (BOOM) <https://boom-core.org/>`__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language.
It serves as a drop-in replacement to the Rocket core given by Rocket Chip.
BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors.
Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”).
Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit.
However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”).
Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages <https://docs.boom-core.org/>`__.

8
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@@ -0,0 +1,8 @@
Hwacha
====================================
The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
Inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures Scale and Maven, we are bringing back elegant, performant, and energy-efficient aspects of vector processing to modern data-parallel architectures.
We propose a new vector-fetch architectural paradigm, which focuses on the following aspects for higher performance, better energy efficiency, and lower complexity.
For more information, please visit the `Hwacha website <http://hwacha.org/>`__.

12
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@@ -0,0 +1,12 @@
Rocket
====================================
`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar core generator that is supported by `SiFive <https://www.sifive.com/>`__.
It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS).
For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units.
Rocket also supports the RISC-V machine, supervisor, and user privilege levels.
A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes.
For more information, please refer to the `GitHub repository <https://github.com/freechipsproject/rocket-chip>`__, `technical report <https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html>`__ or to `this Chisel Community Conference video <https://youtu.be/Eko86PGEoDY>`__.

17
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@@ -0,0 +1,17 @@
Generators
============================
Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL.
This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`).
A standard RTL design is essentially just a single instance of a design coming from a generator.
However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways.
The following pages introduce the generators integrated with the REBAR framework.
.. toctree::
:maxdepth: 2
:caption: Generators:
Rocket
BOOM
Hwacha

340
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@@ -0,0 +1,340 @@
Adding An Accelerator/Device
===============================
Accelerators or custom IO devices can be added to your SoC in several ways:
* MMIO Peripheral (a.k.a TileLink-Attached Accelerator)
* Tightly-Coupled RoCC Accelerator
These approaches differ in the method of the communication between the processor and the custom block.
With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers.
In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space.
Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU.
RoCC coprocessor instructions have the following form.
.. code-block:: none
customX rd, rs1, rs2, funct
The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to.
The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers.
The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other.
Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support.
Integrating into the Generator Build System
-------------------------------------------
While developing, you want to include Chisel code in a submodule so that it can be shared by different projects.
To add a submodule to the REBAR framework, make sure that your project is organized as follows.
.. code-block:: none
yourproject/
build.sbt
src/main/scala/
YourFile.scala
Put this in a git repository and make it accessible.
Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``.
.. code-block:: shell
cd generators/
git submodule add https://git-repository.com/yourproject.git
Then add ``yourproject`` to the REBAR top-level build.sbt file.
.. code-block:: scala
lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip)
You can then import the classes defined in the submodule in a new project if
you add it as a dependency. For instance, if you want to use this code in
the ``example`` project, change the final line in build.sbt to the following.
.. code-block:: scala
lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject)
Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level.
This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files.
MMIO Peripheral
------------------
The easiest way to create a TileLink peripheral is to use the ``TLRegisterRouter``, which abstracts away the details of handling the TileLink protocol and provides a convenient interface for specifying memory-mapped registers.
To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL.
.. code-block:: scala
case class PWMParams(address: BigInt, beatBytes: Int)
trait PWMTLBundle extends Bundle {
val pwmout = Output(Bool())
}
trait PWMTLModule {
val io: PWMTLBundle
implicit val p: Parameters
def params: PWMParams
val w = params.beatBytes * 8
val period = Reg(UInt(w.W))
val duty = Reg(UInt(w.W))
val enable = RegInit(false.B)
// ... Use the registers to drive io.pwmout ...
regmap(
0x00 -> Seq(
RegField(w, period)),
0x04 -> Seq(
RegField(w, duty)),
0x08 -> Seq(
RegField(1, enable)))
}
Once you have these classes, you can construct the final peripheral by extending the ``TLRegisterRouter`` and passing the proper arguments.
The first set of arguments determines where the register router will be placed in the global address map and what information will be put in its device tree entry.
The second set of arguments is the IO bundle constructor, which we create by extending ``TLRegBundle`` with our bundle trait.
The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait.
.. code-block:: scala
class PWMTL(c: PWMParams)(implicit p: Parameters)
extends TLRegisterRouter(
c.address, "pwm", Seq("ucbbar,pwm"),
beatBytes = c.beatBytes)(
new TLRegBundle(c, _) with PWMTLBundle)(
new TLRegModule(c, _, _) with PWMTLModule)
The full module code can be found in ``generators/example/src/main/scala/PWM.scala``.
After creating the module, we need to hook it up to our SoC.
Rocket Chip accomplishes this using the cake pattern.
This basically involves placing code inside traits.
In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait and a module implementation trait.
The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated.
For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar.
.. code-block:: scala
trait HasPeripheryPWM extends HasSystemNetworks {
implicit val p: Parameters
private val address = 0x2000
val pwm = LazyModule(new PWMTL(
PWMParams(address, peripheryBusConfig.beatBytes))(p))
pwm.node := TLFragmenter(
peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}
Note that the ``PWMTL`` class we created from the register router is itself a ``LazyModule``.
Register routers have a TileLink node simply named "node", which we can hook up to the Rocket Chip bus.
This will automatically add address map and device tree entries for the peripheral.
The module implementation trait is where we instantiate our PWM module and connect it to the rest of the SoC.
Since this module has an extra `pwmout` output, we declare that in this trait, using Chisel's multi-IO functionality.
We then connect the ``PWMTL``'s pwmout to the pwmout we declared.
.. code-block:: scala
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
implicit val p: Parameters
val outer: HasPeripheryPWM
val pwmout = IO(Output(Bool()))
pwmout := outer.pwm.module.io.pwmout
}
Now we want to mix our traits into the system as a whole.
This code is from ``generators/example/src/main/scala/Top.scala``.
.. code-block:: scala
class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q)
with PeripheryPWM {
override lazy val module = Module(
new ExampleTopWithPWMModule(p, this))
}
class ExampleTopWithPWMModule(l: ExampleTopWithPWM)
extends ExampleTopModule(l) with HasPeripheryPWMModuleImp
Just as we need separate traits for ``LazyModule`` and module implementation, we need two classes to build the system.
The ``ExampleTop`` classes already have the basic peripherals included for us, so we will just extend those.
The ``ExampleTop`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``).
The ``ExampleTopModule`` class is the actual RTL that gets synthesized.
Finally, we need to add a configuration class in ``generators/example/src/main/scala/Configs.scala`` that tells the ``TestHarness`` to instantiate ``ExampleTopWithPWM`` instead of the default ``ExampleTop``.
.. code-block:: scala
class WithPWM extends Config((site, here, up) => {
case BuildTop => (p: Parameters) =>
Module(LazyModule(new ExampleTopWithPWM()(p)).module)
})
class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig)
Now we can test that the PWM is working. The test program is in ``tests/pwm.c``.
.. code-block:: c
#define PWM_PERIOD 0x2000
#define PWM_DUTY 0x2008
#define PWM_ENABLE 0x2010
static inline void write_reg(unsigned long addr, unsigned long data)
{
volatile unsigned long *ptr = (volatile unsigned long *) addr;
*ptr = data;
}
static inline unsigned long read_reg(unsigned long addr)
{
volatile unsigned long *ptr = (volatile unsigned long *) addr;
return *ptr;
}
int main(void)
{
write_reg(PWM_PERIOD, 20);
write_reg(PWM_DUTY, 5);
write_reg(PWM_ENABLE, 1);
}
This just writes out to the registers we defined earlier.
The base of the module's MMIO region is at 0x2000.
This will be printed out in the address map portion when you generated the verilog code.
Compiling this program with make produces a ``pwm.riscv`` executable.
Now with all of that done, we can go ahead and run our simulation.
.. code-block:: shell
cd verisim
make CONFIG=PWMConfig
./simulator-example-PWMConfig ../tests/pwm.riscv
Adding a RoCC Accelerator
----------------------------
RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class.
Their implementation should extends the ``LazyRoCCModule`` class.
.. code-block:: scala
class CustomAccelerator(opcodes: OpcodeSet)
(implicit p: Parameters) extends LazyRoCC(opcodes) {
override lazy val module = new CustomAcceleratorModule(this)
}
class CustomAcceleratorModule(outer: CustomAccelerator)
extends LazyRoCCModuleImp(outer) {
val cmd = Queue(io.cmd)
// The parts of the command are as follows
// inst - the parts of the instruction itself
// opcode
// rd - destination register number
// rs1 - first source register number
// rs2 - second source register number
// funct
// xd - is the destination register being used?
// xs1 - is the first source register being used?
// xs2 - is the second source register being used?
// rs1 - the value of source register 1
// rs2 - the value of source register 2
...
}
The ``opcodes`` parameter for ``LazyRoCC`` is the set of custom opcodes that will map to this accelerator.
More on this in the next subsection.
The ``LazyRoCC`` class contains two TLOutputNode instances, ``atlNode`` and ``tlNode``.
The former connects into a tile-local arbiter along with the backside of the L1 instruction cache.
The latter connects directly to the L1-L2 crossbar.
The corresponding Tilelink ports in the module implementation's IO bundle are ``atl`` and ``tl``, respectively.
The other interfaces available to the accelerator are ``mem``, which provides access to the L1 cache;
``ptw`` which provides access to the page-table walker;
the ``busy`` signal, which indicates when the accelerator is still handling an instruction;
and the ``interrupt`` signal, which can be used to interrupt the CPU.
Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs.
Adding RoCC accelerator to Config
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter in the configuration.
This takes a sequence of functions producing ``LazyRoCC`` objects, one for each accelerator you wish to add.
For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following.
.. code-block:: scala
class WithCustomAccelerator extends Config((site, here, up) => {
case BuildRoCC => Seq((p: Parameters) => LazyModule(
new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p)))
})
class CustomAcceleratorConfig extends Config(
new WithCustomAccelerator ++ new DefaultExampleConfig)
Adding a DMA port
-------------------
IO devices or accelerators (like a disk or network driver), we may want to have the device write directly to the coherent memory system instead.
To add a device like that, you would do the following.
.. code-block:: scala
class DMADevice(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(TLClientParameters(
name = "dma-device", sourceId = IdRange(0, 1)))
lazy val module = new DMADeviceModule(this)
}
class DMADeviceModule(outer: DMADevice) extends LazyModuleImp(outer) {
val io = IO(new Bundle {
val mem = outer.node.bundleOut
val ext = new ExtBundle
})
// ... rest of the code ...
}
trait HasPeripheryDMA extends HasSystemNetworks {
implicit val p: Parameters
val dma = LazyModule(new DMADevice)
fsb.node := dma.node
}
trait HasPeripheryDMAModuleImp extends LazyMultiIOModuleImp {
val ext = IO(new ExtBundle)
ext <> outer.dma.module.io.ext
}
The ``ExtBundle`` contains the signals we connect off-chip that we get data from.
The DMADevice also has a Tilelink client port that we connect into the L1-L2 crossbar through the front-side buffer (fsb).
The sourceId variable given in the ``TLClientNode`` instantiation determines the range of ids that can be used in acquire messages from this device.
Since we specified [0, 1) as our range, only the ID 0 can be used.

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Configs, Parameters, Mix-ins, and Everything In Between
========================================================
A significant portion of generators in the REBAR framework use the Rocket Chip parameter system.
This parameter system enables for the flexible configuration of the SoC without invasive RTL changes.
In order to use the parameter system correctly, we will use several terms and conventions:
Parameters
--------------------
TODO: Need to explain up, site, field, and other stuff from Henry's thesis.
It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system.
We are still investigating methods to facilitate parameter exploration and discovery.
Configs
---------------------
A *Config* is a collection of multiple generator parameters being set to specific values.
Configs are additive, can override each other, and can be composed of other Configs.
The naming convention for an additive Config is ``With<YourConfigName>``, while the naming convention for a non-additive Config will be ``<YourConfig>``.
Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`).
:numref:`basic-config-example` shows a basic additive Config class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters.
In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design.
.. _basic-config-example:
.. code-block:: scala
class WithMyAcceleratorParams extends Config((site, here, up) => {
case BusWidthBits => 128
case MyAcceleratorKey =>
MyAcceleratorConfig(
rows = 2,
rowBits = 64,
columns = 16,
hartId = 1,
someLength = 256)
})
This next example (:numref:`complex-config-example`) shows a "higher-level" additive Config that uses prior parameters that were set to derive other parameters.
.. _complex-config-example:
.. code-block:: scala
class WithMyMoreComplexAcceleratorConfig extends Config((site, here, up) => {
case BusWidthBits => 128
case MyAcceleratorKey =>
MyAcceleratorConfig(
Rows = 2,
rowBits = site(SystemBusKey).beatBits,
hartId = up(RocketTilesKey, site).length)
})
:numref:`top-level-config` shows a non-additive Config that combines the prior two additive Configs using ``++``.
The additive Configs are applied from the right to left in the list (or bottom to top in the example).
Thus, the order of the parameters being set will first start with the ``DefaultExampleConfig``, then ``WithMyAcceleratorParams``, then ``WithMyMoreComplexAcceleratorConfig``.
.. _top-level-config:
.. code-block:: scala
class SomeAdditiveConfig extends Config(
new WithMyMoreComplexAcceleratorConfig ++
new WithMyAcceleratorParams ++
new DefaultExampleConfig
)
Cake Pattern
-------------------------
A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection).
It is used in the Rocket Chip SoC library and REBAR framework in merging multiple system components and IO interfaces into a large system component.
:numref:`cake-example` shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design.
.. _cake-example:
.. code-block:: scala
class MySoC(implicit p: Parameters) extends RocketSubsystem
with CanHaveMisalignedMasterAXI4MemPort
with HasPeripheryBootROM
with HasNoDebug
with HasPeripherySerial
with HasPeripheryUART
with HasPeripheryIceNIC
{
//Additional top-level specific instantiations or wiring
}
Mix-in
---------------------------
A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses.
The naming convention for an additive mix-in is ``Has<YourMixin>``.
This is show in :numref:`cake-example` where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level.
Additional References
---------------------------
A brief explanation of some of these topics is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY.

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Development Ecosystem
===============================
REBAR Approach
-------------------------------------------
The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts.
REBAR hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research <https://bar.eecs.berkeley.edu/index.html>`__ can coexist and be used together.
REBAR aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC).
Chisel/FIRRTL
-------------------------------------------
One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel.eecs.berkeley.edu/>`__ and the `FIRRTL Compiler <https://freechipsproject.github.io/firrtl/>`__.
Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL.
FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more!
These two tools in combination allow quick design space exploration and development of new RTL.
Generators
-------------------------------------------
Within this repository, all of the Chisel RTL is written as generators.
Generators are parametrized programs designed to generate RTL code based on configuration specifications.
Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects.
Generators allow you to create a family of SoC designs instead of a single instance of a design!

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REBAR Basics
===============================
Generators
-------------------------------------------
The REBAR Framework currently consists of the following RTL generators:
Processor Cores
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
**Rocket**
An in-order RISC-V core.
See :ref:`Rocket` for more information.
**BOOM (Berkeley Out-of-Order Machine)**
An out-of-order RISC-V core.
See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information.
Accelerators
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
**Hwacha**
A decoupled vector architecture co-processor.
Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model.
Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
See :ref:`Hwacha` for more information.
System Components:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
**sifive-blocks**
System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
**AWL (Analog Widget Library)**
Digital components required for integration with high speed serial links.
**testchipip**
A collection of utilities used for testing chips and interfacing them with larger test environments.
.. Fixed Function Accelerators:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
TBD
Tools
-------------------------------------------
**Chisel**
A hardware description library embedded in Scala.
Chisel is used to write RTL generators using meta-programming, by embedding hardware generation primitives in the Scala programming language.
The Chisel compiler elaborates the generator into a FIRRTL output.
See :ref:`Chisel` for more information.
**FIRRTL**
An intermediate representation library for RTL description of digital designs.
FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog.
FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation.
See :ref:`FIRRTL` for more information.
**Barstools**
A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL.
See :ref:`Barstools` for more information.
Toolchains
-------------------------------------------
**riscv-tools**
A collection of software toolchains used to develop and execute software on the RISC-V ISA.
The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel.
The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the REBAR framework.
**esp-tools**
A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.
This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.)
Sims
-------------------------------------------
**verisim (Verilator wrapper)**
Verilator is an open source Verilog simulator.
The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
See :ref:`Verilator` for more information.
**vsim (VCS wrapper)**
VCS is a proprietary Verilog simulator.
Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
See :ref:`VCS` for more information.
**FireSim**
FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud.
FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation.
To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others.
The use of the elastic public cloud enable FireSim to scale simulations up to thousands of nodes.
In order to use FireSim, the repository must be cloned and executed on AWS instances.
See :ref:`FireSim` for more information.
VLSI
-------------------------------------------
**HAMMER**
HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands.
The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints.
The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.).
The HAMMER flow requires access to proprietary EDA tools and process technology libraries.
See :ref:`HAMMER` for more information.

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Running A Simulation
========================================================
REBAR provides support and integration for multiple simulation flows, for various user levels and requirements.
In the majority of cases during a digital design development process, simple software RTL simulation is needed.
When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution.
Software RTL Simulation
------------------------
The REBAR framework provides wrappers for two common software RTL simulators:
the open-source Verilator simulator and the proprietary VCS simulator.
For more information on either of these simulators, please refer to :ref:`Verilator` or :ref:`VCS`.
The following instructions assume at least one of these simulators is installed.
Verilator/VCS Flows
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Verilator is an open-source RTL simulator.
We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
On the other hand, VCS is a proprietary RTL simulator.
We run VCS simulations from within the ``sims/vsim`` directory.
Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS.
First, we will start by entering the Verilator or VCS directory:
.. code-block:: shell
# Enter Verilator directory
cd sims/verisim
# OR
# Enter VCS directory
cd sims/vsim
In order to construct the simulator with our custom design, we run the following command within the simulator directory:
.. code-block:: shell
make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=...
Each of these make variables correspond to a particular part of the design/codebase and are needed so that the make system can correctly build and make a RTL simulation.
The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build.
The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design.
Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class.
The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in.
The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design.
The ``TB`` is the name of the Verilog wrapper that connects the ``TestHarness`` to VCS/Verilator for simulation.
Finally, the ``TOP`` variable is used to distinguish between the top-level of the design and the ``TestHarness`` in our system.
For example, in the normal case, the ``MODEL`` variable specifies the ``TestHarness`` as the top-level of the design.
However, the true top-level design, the SoC being simulated, is pointed to by the ``TOP`` variable.
This separation allows the infrastructure to separate files based on the harness or the SoC top level.
Common configurations of all these variables are packaged using a ``SUB_PROJECT`` make variable.
Therefore, in order to simulate a simple Rocket-based example system we can use:
.. code-block:: shell
make SUB_PROJECT=example
Alternatively, if we would like to simulate a simple BOOM-based example system we can use:
.. code-block:: shell
make SUB_PROJECT=exampleboom
Once the simulator has been constructed, we would like to run RISC-V programs on it.
In the simulation directory, we will find an executable file called ``<...>-<package>-<config>``.
We run this executable with our target RISC-V program as a command line argument in one of two ways.
One, we can directly call the simulator binary or use make to run the binary for us with extra simulation flags.
For example:
.. code-block:: shell
# directly calling the simulation binary
./<...>-<package>-<config> my_program_binary
# using make to do it
make SUB_PROJECT=example BINARY=my_program_binary run-binary
Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``.
For example:
.. code-block:: shell
make SUB_PROJECT=example run-asm-tests
make SUB_PROJECT=example run-bmark-tests
Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option.
Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral and Verilog source files for the build/simulation.
Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``.
FPGA Accelerated Simulation
---------------------------
FireSim enables simulations at 1000x-100000x the speed of standard software simulation.
This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud.
Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine.
To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page.
After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design.
We will work from within the ``sims/firesim`` directory.
TODO: Continue from here

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Getting Started
================================
These guides will walk you through the basics of the REBAR framework:
- First, we will go over the different configurations available.
- Then, we will walk through adding a custom accelerator.
Hit next to get started!
.. toctree::
:maxdepth: 2
:caption: Getting Started:
REBAR-Basics
Configs-Parameters-Mixins
Adding-An-Accelerator-Tutorial
Running-A-Simulation
rebar-generator-mixins

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SoC Generator Config Mix-ins:
==============================
Rocket Chip
-----------------------
+ System-on-Chip
- HasTiles
- HasClockDomainCrossing
- HasResetVectorWire
- HasNoiseMakerIO
+ Basic Core
- HasRocketTiles
- HasRocketCoreParameters
- HasCoreIO
+ Branch Prediction
- HasBtbParameters
+ Additional Compute
- HasFPUCtrlSigs
- HasFPUParameters
- HasLazyRoCC
- HasFpuOpt
+ Memory System
- HasRegMap
- HasCoreMemOp
- HasHellaCache
- HasL1ICacheParameters
- HasICacheFrontendModule
- HasAXI4ControlRegMap
- HasTLControlRegMap
- HasTLBusParams
- HasTLXbarPhy
+ Interrupts
- HasInterruptSources
- HasExtInterrupts
- HasAsyncExtInterrupts
- HasSyncExtInterrupts
+ Periphery
- HasPeripheryDebug
- HasPeripheryBootROM
- HasBuiltInDeviceParams
BOOM
-----------------------
+ Basic Core
- HasBoomTiles
- HasBoomCoreParameters
- HasBoomCoreIO
- HasBoomUOP
- HasRegisterFileIO
+ Branch Prediction
- HasGShareParameters
- HasBoomBTBParameters
+ Memory System
- HasL1ICacheBankedParameters
- HasBoomICacheFrontend
- HasBoomHellaCache
SiFive Blocks
-----------------------
+ Peripherals
- HasPeripheryGPIO
- HasPeripheryI2C
- HasPeripheryMockAON
- HasPeripheryPWM
- HasPeripherySPI
- HasSPIProtocol
- HasSPIEndian
- HasSPILength
- HasSPICSMode
- HasPeripherySPIFlash
- HasPeripheryUART
testchipip
-----------------------
+ Peripherals
- HasPeripheryBlockDevice
- HasPeripherySerial
- HasNoDebug
Icenet
-----------------------
+ Periphery Network Interface Controller
- HasPeripheryIceNIC
AWL
-----------------------
+ IO
- HasEncoding8b10b
- HasTLBidirectionalPacketizer
- HasTLController
- HasGenericTransceiverSubsystem
+ Debug/Testing
- HasBertDebug
- HasPatternMemDebug
- HasBitStufferDebug4Modes
- HasBitReversalDebug

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# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = python -msphinx
SPHINXPROJ = REBAR
SOURCEDIR = .
BUILDDIR = _build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

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Commercial Software RTL Simulators
==============================
VCS
-----------------------
`VCS <https://www.synopsys.com/verification/simulation/vcs.html>`__ is a commercial RTL simulator developed by Synopsys.
It requires commercial licenses.
The REBAR framework can compile and execute simulations using VCS.
VCS simulation will generally compile faster than Verilator simulations.
To run a simulation using VCS, perform the following steps:
Make sure that the VCS simulator is on your ``PATH``.
To compile the example design, run make in the ``sims/vsim`` directory.
This will elaborate the ``DefaultRocketConfig`` in the example project.
An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
This executable is a simulator that has been compiled based on the design that was built.
You can then use this executable to run any compatible RV64 code.
For instance, to run one of the riscv-tools assembly tests.
.. code-block:: shell
./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
If you later create your own project, you can use environment variables to build an alternate configuration.
.. code-block:: shell
make SUB_PROJECT=yourproject
./simulator-<yourproject>-<yourconfig> ...
If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
This will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer.
Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.

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FPGA-Based Simulators
==============================
FireSim
-----------------------
`FireSim <https://fires.im/>`__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1).
FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators.
FireSim also provides additional device models to allow full-system simulation, including memory models and network models.
FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud.
In order to simulate your REBAR design using FireSim, you should follow the following steps:
Follow the initial EC2 setup instructions as detailed in the `FireSim documentation <http://docs.fires.im/en/latest/Initial-Setup/index.html>`__.
Then clone your full REBAR repository onto your Amazon EC2 FireSim manager instance.
Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation <http://docs.fires.im/en/latest/Running-Simulations-Tutorial/index.html>`__.

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Open Source Software RTL Simulators
==============================
Verilator
-----------------------
`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
The REBAR framework can download, build, and execute simulations using Verilator.
To run a simulation using Verilator, perform the following steps:
To compile the example design, run ``make`` in the ``sims/verisim`` directory.
This will elaborate the ``DefaultRocketConfig`` in the example project.
An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
This executable is a simulator that has been compiled based on the design that was built.
You can then use this executable to run any compatible RV64 code.
For instance, to run one of the riscv-tools assembly tests.
.. code-block:: shell
./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
If you later create your own project, you can use environment variables to build an alternate configuration.
.. code-block:: shell
make SUB_PROJECT=yourproject
./simulator-<yourproject>-<yourconfig> ...
If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.

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Simulators
=======================
REBAR provides support and integration for multiple simulation flows, for various user levels and requirements.
In the majority of cases during a digital design development process, a simple software RTL simulation will do.
When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution.
The following pages provide detailed information about the simulation possibilities within the REBAR framework.
.. toctree::
:maxdepth: 2
:caption: Simulators:
Open-Source-Simulators
Commercial-Simulators
FPGA-Based-Simulators

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Barstools
===============================
Barstools is a collection of useful FIRRTL transformations and Compilers to help the build process.
Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more.

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Chisel
===========================
`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
First is the compilation step.
If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions.
Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more.
After the compilation is complete, elaboration begins.
The Chisel generator starts elaboration using the module and configuration classes passed to it.
This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code.
If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library".
However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral!
See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.

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FIRRTL
================================
`FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations.
An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
Once the transformations are done, a Verilog file is emitted and the build process is done.
For more information on please visit their `website <https://freechipsproject.github.io/firrtl/>`__.

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Tools
==============================
The REBAR framework relays heavily on a set of Scala-based tools.
The following pages will introduce them, and how we can use them in order to generate flexible designs.
.. toctree::
:maxdepth: 2
:caption: Tools:
Chisel
FIRRTL
Barstools

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HAMMER
================================
`HAMMER <https://github.com/ucb-bar/hammer>`__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs.
HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `HAMMER paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__.

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VLSI Production
================================
The REBAR framework aim to provide wrappers to a general VLSI flow.
In particular, we aim to support the HAMMER flow.
.. toctree::
:maxdepth: 2
:caption: VLSI Production:
HAMMER

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# -*- coding: utf-8 -*-
#
# REBAR documentation build configuration file, created by
# sphinx-quickstart on Fri Mar 8 11:46:38 2019.
#
# This file is execfile()d with the current directory set to its
# containing dir.
#
# Note that not all possible configuration values are present in this
# autogenerated file.
#
# All configuration values have a default; values that are commented out
# serve to show the default.
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
# -- General configuration ------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
#
# needs_sphinx = '1.0'
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = ['sphinx.ext.autodoc',
'sphinx.ext.intersphinx',
'sphinx.ext.todo',
'sphinx.ext.mathjax',
'sphinx.ext.ifconfig',
'sphinx.ext.viewcode',
'sphinx.ext.githubpages',
'sphinx.ext.autosectionlabel']
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
#
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The master toctree document.
master_doc = 'index'
# General information about the project.
project = u'REBAR'
copyright = u'2019, Berkeley Architecture Research'
author = u'Berkeley Architecture Research'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#
# The short X.Y version.
version = u'0.1'
# The full version, including alpha/beta/rc tags.
release = u'0.1'
# The language for content autogenerated by Sphinx. Refer to documentation
# for a list of supported languages.
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
language = None
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This patterns also effect to html_static_path and html_extra_path
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# The name of the Pygments (syntax highlighting) style to use.
pygments_style = 'sphinx'
# If true, `todo` and `todoList` produce output, else they produce nothing.
todo_include_todos = True
# -- Options for HTML output ----------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'sphinx_rtd_theme'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
#
html_theme_options = {
'collapse_navigation': False,
# 'display_version': True,
# 'navigation_depth': 4,
}
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
# Custom sidebar templates, must be a dictionary that maps document names
# to template names.
#
# This is required for the alabaster theme
# refs: http://alabaster.readthedocs.io/en/latest/installation.html#sidebars
html_sidebars = {
'**': [
'about.html',
'navigation.html',
'relations.html', # needs 'show_related': True theme option to display
'searchbox.html',
'donate.html',
]
}
# -- Options for HTMLHelp output ------------------------------------------
# Output file base name for HTML help builder.
htmlhelp_basename = 'REBARdoc'
# -- Options for LaTeX output ---------------------------------------------
latex_elements = {
# The paper size ('letterpaper' or 'a4paper').
#
# 'papersize': 'letterpaper',
# The font size ('10pt', '11pt' or '12pt').
#
# 'pointsize': '10pt',
# Additional stuff for the LaTeX preamble.
#
# 'preamble': '',
# Latex figure (float) alignment
#
# 'figure_align': 'htbp',
}
# Grouping the document tree into LaTeX files. List of tuples
# (source start file, target name, title,
# author, documentclass [howto, manual, or own class]).
latex_documents = [
(master_doc, 'REBAR.tex', u'REBAR Documentation',
u'Berkeley Architecture Research', 'manual'),
]
# -- Options for manual page output ---------------------------------------
# One entry per manual page. List of tuples
# (source start file, name, description, authors, manual section).
man_pages = [
(master_doc, 'rebar', u'REBAR Documentation',
[author], 1)
]
# -- Options for Texinfo output -------------------------------------------
# Grouping the document tree into Texinfo files. List of tuples
# (source start file, target name, title, author,
# dir menu entry, description, category)
texinfo_documents = [
(master_doc, 'REBAR', u'REBAR Documentation',
author, 'REBAR', 'One line description of project.',
'Miscellaneous'),
]
# Example configuration for intersphinx: refer to the Python standard library.
intersphinx_mapping = {'python' : ('https://docs.python.org/', None),
'boom' : ('https://docs.boom-core.org/en/latest/', None),
'firesim' : ('http://docs.fires.im/en/latest/', None) }

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.. REBAR documentation master file, created by
sphinx-quickstart on Fri Mar 8 11:46:38 2019.
You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
Welcome to REBAR's documentation!
=================================
REBAR is a a framework for designing and evaluating full-system hardware using agile teams.
It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip.
New to REBAR? Jump to the :ref:`Getting Started` page for more info.
.. toctree::
:maxdepth: 3
:caption: Contents:
:numbered:
Getting-Started/index
:maxdepth: 3
:caption: Simulation:
:numbered:
Simulation/index
:maxdepth: 3
:caption: Generators:
:numbered:
Generators/index
:maxdepth: 3
:caption: Tools:
:numbered:
Tools/index
:maxdepth: 3
:caption: VLSI Production:
:numbered:
VLSI/index
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`

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Sphinx==1.7.4
Pygments==2.2.0
sphinx-autobuild
sphinx_rtd_theme==0.2.5b1

1
generators/boom Submodule

Submodule generators/boom added at 2f8c419ff8

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package example
import chisel3._
import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Field, Parameters, Config}
import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC}
import boom.system.{BoomTilesKey}
import testchipip._
import hwacha.{Hwacha}
import sifive.blocks.devices.gpio._
/**
* TODO: Why do we need this?
*/
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
// -----------------------
// Common Parameter Mixins
// -----------------------
/**
* Class to specify where the BootRom file is (from `rebar` top)
*/
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
/**
* Class to add in GPIO
*/
class WithGPIO extends Config((site, here, up) => {
case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 4, includeIOF = false))
})
// -----------------------------------------------
// BOOM and/or Rocket Top Level System Parameter Mixins
// -----------------------------------------------
/**
* Class to specify a "plain" top level BOOM and/or Rocket system
*/
class WithNormalBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new BoomRocketTop()(p)).module)
}
})
/**
* Class to specify a top level BOOM and/or Rocket system with PWM
*/
class WithPWMBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module)
})
/**
* Class to specify a top level BOOM and/or Rocket system with a PWM AXI4
*/
class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module)
})
/**
* Class to specify a top level BOOM and/or Rocket system with a block device
*/
class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
})
/**
* Class to specify a top level BOOM and/or Rocket system with a simulator block device
*/
class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
})
/**
* Class to specify a top level BOOM and/or Rocket system with GPIO
*/
class WithGPIOBoomRocketTop extends Config((site, here, up) => {
case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module)
for (gpio <- top.gpio) {
for (pin <- gpio.pins) {
pin.i.ival := false.B
}
}
top
}
})
// ------------------
// Multi-RoCC Support
// ------------------
/**
* Map from a hartId to a particular RoCC accelerator
*/
case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
/**
* Mixin to enable different RoCCs based on the hartId
*/
class WithMultiRoCC extends Config((site, here, up) => {
case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
})
/**
* Mixin to add Hwachas to cores based on hart
*
* For ex:
* Core 0, 1, 2, 3 have been defined earlier
* with hartIds of 0, 1, 2, 3 respectively
* And you call WithMultiRoCCHwacha(0,1)
* Then Core 0 and 1 will get a Hwacha
*
* @param harts harts to specify which will get a Hwacha
*/
class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
case MultiRoCCKey => {
require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
(i -> Seq((p: Parameters) => {
LazyModule(new Hwacha()(p)).suggestName("hwacha")
}))
}
}
})

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package example
import chisel3._
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks}
import testchipip._
// --------------
// Rocket Configs
// --------------
class BaseRocketConfig extends Config(
new WithBootROM ++
new freechips.rocketchip.system.DefaultConfig)
class DefaultRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseRocketConfig)
class HwachaConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultRocketConfig)
class RoccRocketConfig extends Config(
new WithRoccExample ++
new DefaultRocketConfig)
class PWMRocketConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseRocketConfig)
class PWMAXI4RocketConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseRocketConfig)
class SimBlockDeviceRocketConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseRocketConfig)
class BlockDeviceModelRocketConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseRocketConfig)
class GPIORocketConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseRocketConfig)
class DualCoreRocketConfig extends Config(
new WithNBigCores(2) ++
new DefaultRocketConfig)
class RV32RocketConfig extends Config(
new WithRV32 ++
new DefaultRocketConfig)
class GB1MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 1L) ++
new DefaultRocketConfig)
// ------------
// BOOM Configs
// ------------
class BaseBoomConfig extends Config(
new WithBootROM ++
new boom.system.BoomConfig)
class SmallBaseBoomConfig extends Config(
new WithBootROM ++
new boom.system.SmallBoomConfig)
class DefaultBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseBoomConfig)
class SmallDefaultBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new SmallBaseBoomConfig)
class HwachaBoomConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultBoomConfig)
class RoccBoomConfig extends Config(
new WithRoccExample ++
new DefaultBoomConfig)
class PWMBoomConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseBoomConfig)
class PWMAXI4BoomConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseBoomConfig)
class SimBlockDeviceBoomConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseBoomConfig)
class BlockDeviceModelBoomConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseBoomConfig)
class GPIOBoomConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseBoomConfig)
/**
* Slightly different looking configs since we need to override
* the `WithNBoomCores` with the DefaultBoomConfig params
*/
class DualCoreBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.system.BaseConfig)
class DualCoreSmallBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.common.WithRVC ++
new boom.common.WithSmallBooms ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.system.BaseConfig)
class RV32UnifiedBoomConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.system.SmallRV32UnifiedBoomConfig)
// ---------------------
// BOOM and Rocket Configs
// ---------------------
class BaseBoomAndRocketConfig extends Config(
new WithBootROM ++
new boom.system.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class SmallBaseBoomAndRocketConfig extends Config(
new WithBootROM ++
new boom.system.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.WithSmallBooms ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DefaultBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new BaseBoomAndRocketConfig)
class SmallDefaultBoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new SmallBaseBoomAndRocketConfig)
class HwachaBoomAndRocketConfig extends Config(
new hwacha.DefaultHwachaConfig ++
new DefaultBoomAndRocketConfig)
class RoccBoomAndRocketConfig extends Config(
new WithRoccExample ++
new DefaultBoomAndRocketConfig)
class PWMBoomAndRocketConfig extends Config(
new WithPWMBoomRocketTop ++
new BaseBoomAndRocketConfig)
class PWMAXI4BoomAndRocketConfig extends Config(
new WithPWMAXI4BoomRocketTop ++
new BaseBoomAndRocketConfig)
class SimBlockDeviceBoomAndRocketConfig extends Config(
new WithBlockDevice ++
new WithSimBlockDeviceBoomRocketTop ++
new BaseBoomAndRocketConfig)
class BlockDeviceModelBoomAndRocketConfig extends Config(
new WithBlockDevice ++
new WithBlockDeviceModelBoomRocketTop ++
new BaseBoomAndRocketConfig)
class GPIOBoomAndRocketConfig extends Config(
new WithGPIO ++
new WithGPIOBoomRocketTop ++
new BaseBoomAndRocketConfig)
class DualCoreBoomAndOneRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.system.WithRenumberHarts ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class DualCoreBoomAndOneHwachaRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new WithMultiRoCC ++
new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
new boom.system.WithRenumberHarts ++
new hwacha.DefaultHwachaConfig ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(2) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
class RV32BoomAndRocketConfig extends Config(
new WithNormalBoomRocketTop ++
new WithBootROM ++
new boom.system.WithRenumberHarts ++
new boom.common.WithBoomRV32 ++
new boom.common.WithRVC ++
new boom.common.DefaultBoomConfig ++
new boom.system.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new WithRV32 ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)

90
src/main/scala/example/TestHarness.scala → generators/example/src/main/scala/Generator.scala
View File

@@ -1,46 +1,22 @@
package example
import scala.collection.mutable.LinkedHashSet
import chisel3._
import chisel3.experimental._
import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem.{RocketTilesKey}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.util.GeneratorApp
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.tile.{XLen}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.tile.XLen
import scala.collection.mutable.LinkedHashSet
case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]]
class TestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
val dut = p(BuildTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.l2_frontend_bus_axi4.foreach(axi => {
axi.tieoff()
experimental.DataMirror.directionOf(axi.ar.ready) match {
case core.ActualDirection.Input =>
axi.r.bits := DontCare
axi.b.bits := DontCare
case core.ActualDirection.Output =>
axi.aw.bits := DontCare
axi.ar.bits := DontCare
axi.w.bits := DontCare
}
})
io.success := dut.connectSimSerial()
}
import boom.system.{BoomTilesKey, BoomTestSuites}
object Generator extends GeneratorApp {
//Copied from rocketchip
val rv64RegrTestNames = LinkedHashSet(
"rv64ud-v-fcvt",
"rv64ud-p-fdiv",
@@ -77,11 +53,14 @@ object Generator extends GeneratorApp {
"rv32mi-p-sbreak",
"rv32ui-p-sll")
override def addTestSuites {
import freechips.rocketchip.system.DefaultTestSuites._
val xlen = params(XLen)
// TODO: for now only generate tests for the first core in the first subsystem
// TODO: for now only generate tests for the first rocket/boom tile in the subsystem
// TODO: support heterogenous systems?
// rocket specific tests
params(RocketTilesKey).headOption.map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
@@ -114,8 +93,47 @@ object Generator extends GeneratorApp {
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
// boom specific tests
params(BoomTilesKey).headOption.map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv32ud))
}
} else if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv64ud))
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuite(rv32udBenchmarks)
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
} else {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
// Include our BOOM-specific overrides.
val (rvi, rvu) =
if (xlen == 64) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites(rvu.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
rv64RegrTestNames -= "rv64mi-p-breakpoint" // TODO: breakpoints not implemented yet
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
//End copied from rocketchip
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl
generateAnno

0
src/main/scala/example/PWM.scala → generators/example/src/main/scala/PWM.scala
View File

45
generators/example/src/main/scala/TestHarness.scala Normal file
View File

@@ -0,0 +1,45 @@
package example
import chisel3._
import chisel3.experimental._
import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper}
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.util.GeneratorApp
// --------------------------
// BOOM and/or Rocket Test Harness
// --------------------------
case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
class BoomRocketTestHarness(implicit val p: Parameters) extends Module {
val io = IO(new Bundle {
val success = Output(Bool())
})
// force Chisel to rename module
override def desiredName = "TestHarness"
val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
dut.debug := DontCare
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.l2_frontend_bus_axi4.foreach(axi => {
axi.tieoff()
experimental.DataMirror.directionOf(axi.ar.ready) match {
case core.ActualDirection.Input =>
axi.r.bits := DontCare
axi.b.bits := DontCare
case core.ActualDirection.Output =>
axi.aw.bits := DontCare
axi.ar.bits := DontCare
axi.w.bits := DontCare
}
})
io.success := dut.connectSimSerial()
}

69
generators/example/src/main/scala/Top.scala Normal file
View File

@@ -0,0 +1,69 @@
package example
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
import testchipip._
import sifive.blocks.devices.gpio._
// -------------------------------
// BOOM and/or Rocket Top Level Systems
// -------------------------------
class BoomRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem
with HasNoDebug
with HasPeripherySerial {
override lazy val module = new BoomRocketTopModule(this)
}
class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l)
with HasNoDebugModuleImp
with HasPeripherySerialModuleImp
with DontTouch
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop
with HasPeripheryPWMTL {
override lazy val module = new BoomRocketTopWithPWMTLModule(this)
}
class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l)
with HasPeripheryPWMTLModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop
with HasPeripheryPWMAXI4 {
override lazy val module = new BoomRocketTopWithPWMAXI4Module(this)
}
class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l)
with HasPeripheryPWMAXI4ModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop
with HasPeripheryBlockDevice {
override lazy val module = new BoomRocketTopWithBlockDeviceModule(this)
}
class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l)
with HasPeripheryBlockDeviceModuleImp
//---------------------------------------------------------------------------------------------------------
class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
with HasPeripheryGPIO {
override lazy val module = new BoomRocketTopWithGPIOModule(this)
}
class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
extends BoomRocketTopModule(l)
with HasPeripheryGPIOModuleImp

1
generators/hwacha Submodule

Submodule generators/hwacha added at ff4605f5d1

0
rocket-chip → generators/rocket-chip
View File

1
generators/sifive-blocks Submodule

Submodule generators/sifive-blocks added at 24dd537894

0
testchipip → generators/testchipip
View File

1
generators/utilities/src/main/resources/bootrom Symbolic link
View File

@@ -0,0 +1 @@
../../../../rocket-chip/bootrom

0
src/main/resources/project-template/csrc/emulator.cc → generators/utilities/src/main/resources/csrc/emulator.cc
View File

6
src/main/scala/example/Simulator.scala → generators/utilities/src/main/scala/Simulator.scala
View File

@@ -1,4 +1,4 @@
package example
package utilities
import java.io.File
@@ -90,7 +90,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
"/vsrc/EICG_wrapper.v",
) ++ (sim match { // simulator specific files to include
case VerilatorSimulator => Seq(
"/project-template/csrc/emulator.cc",
"/csrc/emulator.cc",
"/csrc/verilator.h",
)
case VCSSimulator => Seq(
@@ -101,6 +101,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
def writeBootrom(): Unit = {
firrtl.FileUtils.makeDirectory("./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
writeResource("/bootrom/bootrom.img", "./bootrom/")
}
def writeFiles(cfg: GenerateSimConfig): Unit = {

18
project/plugins.sbt
View File

@@ -1 +1,17 @@
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns)
resolvers += Classpaths.sbtPluginReleases
resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"

38
scripts/build-toolchains.sh Executable file
View File

@@ -0,0 +1,38 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
unamestr=$(uname)
RDIR=$(pwd)
: ${REBAR_DIR:=$(pwd)} #default value is the PWD unless overridden
if [ $# -ne 0 ]; then
TOOLCHAIN=$1
if [ $1 == "riscv" ]; then
TOOLCHAIN="riscv-tools"
elif [ $1 == "hwacha" ]; then
TOOLCHAIN="esp-tools"
fi
else
TOOLCHAIN="riscv-tools"
fi
INSTALL_DIR="$TOOLCHAIN-install"
mkdir -p "$(pwd)/$INSTALL_DIR"
RISCV="$(pwd)/$INSTALL_DIR"
# install risc-v tools
export RISCV="$RISCV"
git -C $REBAR_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8
cd "$REBAR_DIR/toolchains/$TOOLCHAIN"
export MAKEFLAGS="-j16"
./build.sh
cd $RDIR
echo "export RISCV=$RISCV" > env.sh
echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh
echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh
echo "Toolchain Build Complete!"

17
scripts/gen-tags.sh Executable file
View File

@@ -0,0 +1,17 @@
#!/usr/bin/env bash
# run this script in the main rebar directory to generate ctags for all relevant repos
# note: this requires exuberant-ctags
# tested with: Exuberant Ctags 5.8
# instructions:
# cd /path/to/rebar/
# ./scripts/gen-tags.sh
#
# input:
# * nothing
#
# output:
# * tags file in the directory that this was called in
# ctags wrapper
ctags -R --exclude=@.ctagsignore --links=no

19
scripts/init-submodules-no-riscv-tools.sh Executable file
View File

@@ -0,0 +1,19 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
unamestr=$(uname)
RDIR=$(pwd)
# ignore riscv-tools for submodule init recursive
# you must do this globally (otherwise riscv-tools deep
# in the submodule tree will get pulled anyway
git config --global submodule.riscv-tools.update none
git config --global submodule.esp-tools.update none
git config --global submodule.experimental-blocks.update none
git submodule update --init --recursive #--jobs 8
# unignore riscv-tools,catapult-shell2 globally
git config --global --unset submodule.riscv-tools.update
git config --global --unset submodule.experimental-blocks.update

31
scripts/regression.sh Executable file
View File

@@ -0,0 +1,31 @@
#!/bin/bash
# NOTE: TEMPORARY UNTIL CI IS ONLINE
# Run by just giving the test to run (run-bmark-tests | run-asm-tests)
# Runs in vsim and verisim
set -ex
set -euo pipefail
cd sims/vsim/
make SUB_PROJECT=rocketchip CONFIG=DefaultConfig
make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1
make SUB_PROJECT=boom CONFIG=BoomConfig
make SUB_PROJECT=boom CONFIG=BoomConfig $1
make SUB_PROJECT=example CONFIG=DefaultRocketConfig
make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1
make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig
make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1
cd ../verisim/
make SUB_PROJECT=rocketchip CONFIG=DefaultConfig
make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1
make SUB_PROJECT=boom CONFIG=BoomConfig
make SUB_PROJECT=boom CONFIG=BoomConfig $1
make SUB_PROJECT=example CONFIG=DefaultRocketConfig
make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1
make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig
make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1

3
verisim/.gitignore → sims/verisim/.gitignore vendored
View File

@@ -1,3 +1,4 @@
*
!.gitignore
!Makefile
!Makefrag-verilator
!verilator.mk

102
sims/verisim/Makefile Normal file
View File

@@ -0,0 +1,102 @@
#########################################################################################
# verilator makefile
#########################################################################################
#########################################################################################
# general path variables
#########################################################################################
base_dir=$(abspath ../..)
sim_dir=$(abspath .)
#########################################################################################
# include shared variables
#########################################################################################
include $(base_dir)/variables.mk
#########################################################################################
# name of simulator (used to generate *.f arguments file)
#########################################################################################
sim_name = verilator
#########################################################################################
# vcs simulator types and rules
#########################################################################################
sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
PERMISSIVE_ON=
PERMISSIVE_OFF=
.PHONY: default debug
default: $(sim)
debug: $(sim_debug)
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
include $(sim_dir)/verilator.mk
#########################################################################################
# verilator build paths and file names
#########################################################################################
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(VLOG_MODEL).h
model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
model_mk = $(model_dir)/V$(VLOG_MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
#########################################################################################
# build makefile fragment that builds the verilator sim rules
#########################################################################################
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk
#########################################################################################
# helper rules to run simulator with debug
#########################################################################################
run-binary-debug: $(sim_debug)
$(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# create a verisim vpd rule
#########################################################################################
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
rm -f $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null &
$(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $<
#########################################################################################
# general cleanup rule
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)/* $(sim_prefix)-*

50
sims/verisim/verilator.mk Normal file
View File

@@ -0,0 +1,50 @@
#########################################################################################
# verilator installation makefrag
#########################################################################################
#########################################################################################
# verilator version, binary, and path
#########################################################################################
VERILATOR_VERSION=4.008
VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
#########################################################################################
# build and install our own verilator to work around versioning issues
#########################################################################################
$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
touch $@
.PHONY:
verilator_install: $(INSTALLED_VERILATOR)
$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
touch $@
$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
mkdir -p $(dir $@)
cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
rm -rf $(dir $@)
mkdir -p $(dir $@)
cat $^ | tar -xz --strip-components=1 -C $(dir $@)
touch $@
verilator/verilator-$(VERILATOR_VERSION).tar.gz:
mkdir -p $(dir $@)
wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
#########################################################################################
# verilator binary and flags
#########################################################################################
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \
-Wno-STMTDLY --x-assign unique \
-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR"

3
vsim/.gitignore → sims/vsim/.gitignore vendored
View File

@@ -1,2 +1,3 @@
!Makefile
*
!.gitignore
!Makefile

106
sims/vsim/Makefile Normal file
View File

@@ -0,0 +1,106 @@
#########################################################################################
# vcs makefile
#########################################################################################
#########################################################################################
# general path variables
#########################################################################################
base_dir=$(abspath ../..)
sim_dir=$(abspath .)
#########################################################################################
# include shared variables
#########################################################################################
include $(base_dir)/variables.mk
#########################################################################################
# name of simulator (used to generate *.f arguments file)
#########################################################################################
sim_name = vcs
#########################################################################################
# vcs simulator types and rules
#########################################################################################
sim_prefix = simv
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
.PHONY: default debug
default: $(sim)
debug: $(sim_debug)
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
#########################################################################################
# vcs binary and arguments
#########################################################################################
VCS = vcs -full64
VCS_CC_OPTS = \
-CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
$(RISCV)/lib/libfesvr.so
VCS_NONCC_OPTS = \
+lint=all,noVCDE,noONGS,noUI \
-error=PCWM-L \
-timescale=1ns/10ps \
-quiet \
+rad \
+v2k \
+vcs+lic+wait \
+vc+list \
-f $(sim_top_blackboxes) \
-f $(sim_harness_blackboxes) \
-f $(sim_dotf) \
-sverilog \
+incdir+$(build_dir) \
+define+CLOCK_PERIOD=1.0 \
$(sim_vsrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+libext+.v
VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
#########################################################################################
# vcs simulator rules
#########################################################################################
$(sim): $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp
$(sim_debug) : $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG -debug_pp
#########################################################################################
# helper rules to run simulator with debug
#########################################################################################
run-binary-debug: $(sim_debug)
$(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# create a vcs vpd rule
#########################################################################################
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
$(sim_debug) $(PERMISSIVE_ON) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $<
#########################################################################################
# general cleanup rule
#########################################################################################
.PHONY: clean
clean:
rm -rf $(gen_dir)/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h

97
src/main/scala/example/Configs.scala
View File

@@ -1,97 +0,0 @@
package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize}
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.tile.XLen
import testchipip._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => BootROMParams(
contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")
})
object ConfigValName {
implicit val valName = ValName("TestHarness")
}
import ConfigValName._
class WithExampleTop extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
Module(LazyModule(new ExampleTop()(p)).module)
}
})
class WithPWM extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new ExampleTopWithPWMTL()(p)).module)
})
class WithPWMAXI4 extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
Module(LazyModule(new ExampleTopWithPWMAXI4()(p)).module)
})
class WithBlockDeviceModel extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
top.connectBlockDeviceModel()
top
}
})
class WithSimBlockDevice extends Config((site, here, up) => {
case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
val top = Module(LazyModule(new ExampleTopWithBlockDevice()(p)).module)
top.connectSimBlockDevice(clock, reset)
top
}
})
class BaseExampleConfig extends Config(
new WithBootROM ++
new freechips.rocketchip.system.DefaultConfig)
class DefaultExampleConfig extends Config(
new WithExampleTop ++ new BaseExampleConfig)
class RoccExampleConfig extends Config(
new WithRoccExample ++ new DefaultExampleConfig)
class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig)
class PWMAXI4Config extends Config(new WithPWMAXI4 ++ new BaseExampleConfig)
class SimBlockDeviceConfig extends Config(
new WithBlockDevice ++ new WithSimBlockDevice ++ new BaseExampleConfig)
class BlockDeviceModelConfig extends Config(
new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
class WithFourTrackers extends WithNBlockDeviceTrackers(4)
class WithTwoMemChannels extends WithNMemoryChannels(2)
class WithFourMemChannels extends WithNMemoryChannels(4)
// 16GB of off chip memory
class BigMemoryConfig extends Config(
new WithExtMemSize((1<<30) * 16L) ++ new DefaultExampleConfig)
// 1GB of off chip memory
class GB1MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 1L) ++ new DefaultExampleConfig)
class GB2MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 2L) ++ new DefaultExampleConfig)
class GB4MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 4L) ++ new DefaultExampleConfig)
class GB8MemoryConfig extends Config(
new WithExtMemSize((1<<30) * 8L) ++ new DefaultExampleConfig)
class DualCoreConfig extends Config(
// Core gets tacked onto existing list
new WithNBigCores(2) ++ new DefaultExampleConfig)
class RV32ExampleConfig extends Config(
new WithRV32 ++ new DefaultExampleConfig)

53
src/main/scala/example/Top.scala
View File

@@ -1,53 +0,0 @@
package example
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
import testchipip._
class ExampleTop(implicit p: Parameters) extends ExampleRocketSystem //RocketSubsystem
with CanHaveMasterAXI4MemPort
with HasPeripheryBootROM
// with HasSystemErrorSlave
// with HasSyncExtInterrupts
with HasNoDebug
with HasPeripherySerial {
override lazy val module = new ExampleTopModule(this)
}
class ExampleTopModule[+L <: ExampleTop](l: L) extends ExampleRocketSystemModuleImp(l) // RocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
// with HasExtInterruptsModuleImp
with HasNoDebugModuleImp
with HasPeripherySerialModuleImp
with DontTouch
class ExampleTopWithPWMTL(implicit p: Parameters) extends ExampleTop
with HasPeripheryPWMTL {
override lazy val module = new ExampleTopWithPWMTLModule(this)
}
class ExampleTopWithPWMTLModule(l: ExampleTopWithPWMTL)
extends ExampleTopModule(l) with HasPeripheryPWMTLModuleImp
class ExampleTopWithPWMAXI4(implicit p: Parameters) extends ExampleTop
with HasPeripheryPWMAXI4 {
override lazy val module = new ExampleTopWithPWMAXI4Module(this)
}
class ExampleTopWithPWMAXI4Module(l: ExampleTopWithPWMAXI4)
extends ExampleTopModule(l) with HasPeripheryPWMAXI4ModuleImp
class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
with HasPeripheryBlockDevice {
override lazy val module = new ExampleTopWithBlockDeviceModule(this)
}
class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
extends ExampleTopModule(l)
with HasPeripheryBlockDeviceModuleImp

1
toolchains/esp-tools Submodule

Submodule toolchains/esp-tools added at aba7bd828d

1
toolchains/riscv-tools Submodule

Submodule toolchains/riscv-tools added at bce7b5e363

0
barstools → tools/barstools
View File

1
tools/chisel3 Submodule

Submodule tools/chisel3 added at e1aa5f3f5c

1
tools/firrtl Submodule

Submodule tools/firrtl added at 99ae1d6649

1
tools/torture Submodule

Submodule tools/torture added at 59b0f0f224

165
variables.mk Normal file
View File

@@ -0,0 +1,165 @@
#########################################################################################
# makefile variables shared across multiple makefiles
#########################################################################################
#########################################################################################
# variables to invoke the generator
# descriptions:
# SBT_PROJECT = the SBT project that you should find the classes/packages in
# MODEL = the top level module of the project in Chisel (normally the harness)
# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
# MODEL_PACKAGE = the scala package to find the MODEL in
# CONFIG = the configuration class to give the parameters for the project
# CONFIG_PACKAGE = the scala package to find the CONFIG class
# GENERATOR_PACKAGE = the scala package to find the Generator class in
# TB = wrapper over the TestHarness needed to simulate in a verilog simulator
# TOP = top level module of the project (normally the module instantiated by the harness)
#
# project specific:
# SUB_PROJECT = use the specific subproject default variables
#########################################################################################
#########################################################################################
# subproject overrides
# description:
# - make it so that you only change 1 param to change most or all of them!
# - mainly intended for quick developer setup for common flags
#########################################################################################
SUB_PROJECT ?= example
ifeq ($(SUB_PROJECT),example)
SBT_PROJECT ?= example
MODEL ?= BoomRocketTestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= $(SBT_PROJECT)
CONFIG ?= DefaultRocketConfig
CONFIG_PACKAGE ?= $(SBT_PROJECT)
GENERATOR_PACKAGE ?= $(SBT_PROJECT)
TB ?= TestDriver
TOP ?= BoomRocketTop
endif
# for BOOM developers
ifeq ($(SUB_PROJECT),boom)
SBT_PROJECT ?= boom
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= boom.system
CONFIG ?= BoomConfig
CONFIG_PACKAGE ?= boom.system
GENERATOR_PACKAGE ?= boom.system
TB ?= TestDriver
TOP ?= ExampleBoomAndRocketSystem
endif
# for Rocket-chip developers
ifeq ($(SUB_PROJECT),rocketchip)
SBT_PROJECT ?= rebarrocketchip
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= freechips.rocketchip.system
CONFIG ?= DefaultConfig
CONFIG_PACKAGE ?= freechips.rocketchip.system
GENERATOR_PACKAGE ?= freechips.rocketchip.system
TB ?= TestDriver
TOP ?= ExampleRocketSystem
endif
# for Hwacha developers
ifeq ($(SUB_PROJECT),hwacha)
SBT_PROJECT ?= hwacha
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= freechips.rocketchip.system
CONFIG ?= HwachaConfig
CONFIG_PACKAGE ?= hwacha
GENERATOR_PACKAGE ?= hwacha
TB ?= TestDriver
TOP ?= ExampleRocketSystem
endif
#########################################################################################
# path to rocket-chip and testchipip
#########################################################################################
ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
TESTCHIP_DIR = $(base_dir)/generators/testchipip
REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl
#########################################################################################
# names of various files needed to compile and run things
#########################################################################################
long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
# match the long_name to what the specific generator will output
ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system)
long_name=$(CONFIG_PACKAGE).$(CONFIG)
endif
ifeq ($(GENERATOR_PACKAGE),hwacha)
long_name=$(MODEL_PACKAGE).$(CONFIG)
endif
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
TOP_FIR ?= $(build_dir)/$(long_name).top.fir
TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir
SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v
SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir
sim_dotf ?= $(build_dir)/sim_files.f
sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
#########################################################################################
# java arguments used in sbt
#########################################################################################
JAVA_ARGS ?= -Xmx8G -Xss8M -XX:MaxPermSize=256M
#########################################################################################
# default sbt launch command
#########################################################################################
SCALA_VERSION=2.12.4
SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
#########################################################################################
# output directory for tests
#########################################################################################
output_dir=$(sim_dir)/output/$(long_name)
#########################################################################################
# helper variables to run binaries
#########################################################################################
BINARY ?=
SIM_FLAGS ?= +max-cycles=$(timeout_cycles)
sim_out_name = $(notdir $(basename $(BINARY))).$(long_name)
#########################################################################################
# build output directory for compilation
#########################################################################################
gen_dir=$(sim_dir)/generated-src
build_dir=$(gen_dir)/$(long_name)
#########################################################################################
# vsrcs needed to run projects
#########################################################################################
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
#########################################################################################
# sources needed to run simulators
#########################################################################################
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(SMEMS_FILE) \
$(HARNESS_SMEMS_FILE)
#########################################################################################
# assembly/benchmark variables
#########################################################################################
timeout_cycles = 10000000
bmark_timeout_cycles = 100000000

87
verisim/Makefile
View File

@@ -1,87 +0,0 @@
base_dir=$(abspath ..)
sim_dir=$(abspath .)
PROJECT ?= example
MODEL ?= TestHarness
CONFIG ?= DefaultExampleConfig
CFG_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= ExampleTop
sim_name = verilator
sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
default: $(sim)
debug: $(sim_debug)
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag-verilator
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d
endif
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(HARNESS_SMEMS_FILE) \
$(SMEMS_FILE)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(MODEL).h
model_header_debug = $(model_dir_debug)/V$(MODEL).h
model_mk = $(model_dir)/V$(MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
$(sim): $(model_mk)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@
$(sim_debug): $(model_mk_debug)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
$(output_dir)/%.out: $(output_dir)/% $(sim)
$(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
$(output_dir)/%.run: $(output_dir)/% $(sim)
$(sim) +max-cycles=1000000 $< && touch $@
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
rm -f $@.vcd && mkfifo $@.vcd
vcd2vpd $@.vcd $@ > /dev/null &
$(sim_debug) -v$@.vcd +max-cycles=1000000 $<
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
clean:
rm -rf generated-src ./simulator-*

34
verisim/Makefrag-verilator
View File

@@ -1,34 +0,0 @@
# Build and install our own Verilator, to work around versionining issues.
VERILATOR_VERSION=3.920
VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
touch $@
$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
touch $@
$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
mkdir -p $(dir $@)
cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
rm -rf $(dir $@)
mkdir -p $(dir $@)
cat $^ | tar -xz --strip-components=1 -C $(dir $@)
touch $@
verilator/verilator-$(VERILATOR_VERSION).tar.gz:
mkdir -p $(dir $@)
wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
# Run Verilator to produce a fast binary to emulate this circuit.
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \
-Wno-STMTDLY --x-assign unique \
-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"

83
vsim/Makefile
View File

@@ -1,83 +0,0 @@
base_dir=$(abspath ..)
sim_dir=$(abspath .)
PROJECT ?= example
MODEL ?= TestHarness
CONFIG ?= DefaultExampleConfig
CFG_PROJECT ?= $(PROJECT)
TB ?= TestDriver
TOP ?= ExampleTop
sim_name = vcs
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
default: $(simv)
debug: $(simv_debug)
include $(base_dir)/Makefrag
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(build_dir)/$(long_name).d
endif
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
sim_vsrcs = \
$(VERILOG_FILE) \
$(HARNESS_FILE) \
$(HARNESS_SMEMS_FILE) \
$(SMEMS_FILE)
VCS = vcs -full64
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
-f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -f $(sim_dotf) \
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+libext+.v \
verilog: $(sim_vsrcs)
$(simv): $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-debug_pp
$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+define+DEBUG -debug_pp
$(output_dir)/%.out: $(output_dir)/% $(simv)
$(simv) +permissive -q +ntb_random_seed_automatic +verbose +max-cycles=1000000 +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@
$(output_dir)/%.run: $(output_dir)/% $(simv)
$(simv) +permissive -q +ntb_random_seed_automatic +max-cycles=1000000 +permissive-off $< && touch $@
$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
$(simv_debug) +permissive -q +ntb_random_seed_automatic +vcdplusfile=$@ +max-cycles=1000000 +permissive-off $<
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
clean:
rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
.PHONY: clean