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[clocks] IdealizedPll -> DividerOnlyClockGenerator

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This commit is contained in:
David Biancolin
2020-09-29 17:33:49 -07:00
parent 5b414f5829
commit ebfe3103a4
2 changed files with 14 additions and 14 deletions
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12
generators/chipyard/src/main/scala/Clocks.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.util.{ResetCatchAndSync, Pow2ClockDivider}
import barstools.iocell.chisel._
import chipyard.clocking.{IdealizedPLL, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
import chipyard.clocking.{DividerOnlyClockGenerator, ClockGroupNamePrefixer, ClockGroupFrequencySpecifier}
/**
* Chipyard provides three baseline, top-level reset schemes, set using the
@@ -79,12 +79,12 @@ object GenerateReset {
}
case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.idealizedPLL)
/**
case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGenerators.dividerOnlyClockGenerator)
/*
* This is a Seq of assignment functions, that accept a clock name and return an optional frequency.
* Functions that appear later in this seq have higher precedence that earlier ones.
* If no function returns a non-empty value, the value specified in
* [[DefaultClockFrequencyKey]] will be used -- DFU.
* [[DefaultClockFrequencyKey]] will be used.
*/
case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty)
case object DefaultClockFrequencyKey extends Field[Double]()
@@ -100,7 +100,7 @@ class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((si
})
object ClockingSchemeGenerators {
val idealizedPLL: ChipTop => Unit = { chiptop =>
val dividerOnlyClockGenerator: ChipTop => Unit = { chiptop =>
implicit val p = chiptop.p
// Requires existence of undriven asyncClockGroups in subsystem
@@ -116,7 +116,7 @@ object ClockingSchemeGenerators {
val referenceClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
(aggregator
:= ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
:= IdealizedPLL()
:= DividerOnlyClockGenerator()
:= referenceClockSource)

16
generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala → generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
View File

@@ -26,12 +26,12 @@ object FrequencyUtils {
}
}
class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters]) {
class SimplePllConfiguration(name: String, val sinks: Seq[ClockSinkParameters]) {
val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz
val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*)
private val preamble = s"""
|${pllName} Frequency Summary
|${name} Frequency Summary
| Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin
private val outputSummaries = sinkDividerMap.map { case (sink, division) =>
val requested = sink.take.get.freqMHz
@@ -40,11 +40,11 @@ class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters
}
val summaryString = preamble + outputSummaries.mkString("\n")
ElaborationArtefacts.add(s"${pllName}.freq-summary", summaryString)
ElaborationArtefacts.add(s"${name}.freq-summary", summaryString)
println(summaryString)
}
case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockImp, ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { u =>
@@ -64,8 +64,8 @@ case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
* frequency.
*/
class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
val node = IdealizedPLLNode(pllName)
class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
val node = DividerOnlyClockGeneratorNode(pllName)
lazy val module = new LazyRawModuleImp(this) {
require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator")
@@ -92,6 +92,6 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex
}
}
object IdealizedPLL {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new IdealizedPLL(valName.name)).node
object DividerOnlyClockGenerator {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new DividerOnlyClockGenerator(valName.name)).node
}