Fft changes (#15)
* modified CustomBundle to also apply on Int * programmatic bundle should take T <: Data instead of Data * turns out indexedElements doesn't synthesize * had to change a bunch of files to get clk/pads compiling again with recent firrtl mods
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@@ -21,7 +21,7 @@ class ClkSrcTransform extends Transform with SimpleRun {
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InferTypes,
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new CreateClkConstraints(clkModAnnos, clkPortAnnos, targetDir)
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)
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state.copy(state = runPasses(state.circuit, passSeq), outputForm = outputForm)
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state.copy(circuit = runPasses(state.circuit, passSeq))
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}
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}
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}
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@@ -89,7 +89,7 @@ class CreateClkConstraints(
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}).toSet
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val inlineTransform = new InlineInstances
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val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set()).circuit
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val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), None).circuit
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val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError)
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@@ -16,7 +16,7 @@ class AddIOPadsTransform extends Transform with SimpleRun {
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val collectedAnnos = HasPadAnnotation(getMyAnnotations(state))
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collectedAnnos match {
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// Transform not used
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case None => CircuitState(state.circuit, LowForm)
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case None => state
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case Some(x) =>
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val techLoc = (new TechnologyLocation).get(state)
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// Get foundry pad templates from yaml
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@@ -45,11 +45,10 @@ class AddIOPadsTransform extends Transform with SimpleRun {
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)
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// Expects BlackBox helper to be run after to inline pad Verilog!
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val prevAnnos = state.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations
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val cs = CircuitState(
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runPasses(circuitWithBBs, passSeq),
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LowForm,
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Some(AnnotationMap(prevAnnos ++ bbAnnotations))
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)
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val cs = state.copy(
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circuit = runPasses(circuitWithBBs, passSeq),
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annotations = Some(AnnotationMap(prevAnnos ++ bbAnnotations)))
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// TODO: *.f file is overwritten on subsequent executions, but it doesn't seem to be used anywhere?
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(new firrtl.transforms.BlackBoxSourceHelper).execute(cs)
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}
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@@ -3,22 +3,24 @@ package barstools.tapeout.transforms
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import chisel3._
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import scala.collection.immutable.ListMap
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final class CustomBundle(elts: (String, Data)*) extends Record {
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final class CustomBundle[T <: Data](elts: (String, T)*) extends Record {
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val elements = ListMap(elts map { case (field, elt) => field -> elt.chiselCloneType }: _*)
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def apply(elt: String): Data = elements(elt)
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def apply(elt: String): T = elements(elt)
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def apply(elt: Int): T = elements(elt.toString)
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override def cloneType = (new CustomBundle(elements.toList: _*)).asInstanceOf[this.type]
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}
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final class CustomIndexedBundle(elts: (Int, Data)*) extends Record {
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final class CustomIndexedBundle[T <: Data](elts: (Int, T)*) extends Record {
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// Must be String, Data
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val elements = ListMap(elts map { case (field, elt) => field.toString -> elt.chiselCloneType }: _*)
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def indexedElements = ListMap(elts map { case (field, elt) => field -> elt.chiselCloneType }: _*)
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def apply(elt: Int): Data = elements(elt.toString)
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// TODO: Make an equivalent to the below work publicly
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private def indexedElements = ListMap(elts map { case (field, elt) => field -> elt.chiselCloneType }: _*)
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def apply(elt: Int): T = elements(elt.toString)
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override def cloneType = (new CustomIndexedBundle(indexedElements.toList: _*)).asInstanceOf[this.type]
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}
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object CustomIndexedBundle {
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def apply(gen: Data, idxs: Seq[Int]) = new CustomIndexedBundle(idxs.map(_ -> gen): _*)
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def apply[T <: Data](gen: T, idxs: Seq[Int]) = new CustomIndexedBundle(idxs.map(_ -> gen): _*)
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// Allows Vecs of elements of different types/widths
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def apply(gen: Seq[Data]) = new CustomIndexedBundle(gen.zipWithIndex.map{ case (elt, field) => field -> elt }: _*)
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def apply[T <: Data](gen: Seq[T]) = new CustomIndexedBundle(gen.zipWithIndex.map{ case (elt, field) => field -> elt }: _*)
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}
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@@ -3,7 +3,6 @@
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package barstools.tapeout.transforms
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import chisel3._
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import chisel3.util.RegInit
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import firrtl._
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import org.scalatest.{FreeSpec, Matchers}
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