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Merge pull request #1252 from ucb-bar/fsdb

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Default VCS simulators should generate FSDB
This commit is contained in:
Jerry Zhao
2022-10-16 14:15:40 -07:00
committed by GitHub
parent d6fa88c67d d83ba0c19b
commit fb2f83b90c
4 changed files with 8 additions and 8 deletions
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2
docs/VLSI/ASAP7-Tutorial.rst
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@@ -152,7 +152,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
Power/Rail Analysis
^^^^^^^^^^^^^^^^^^^

2
docs/VLSI/Sky130-Commercial-Tutorial.rst
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@@ -156,7 +156,7 @@ Simulation with VCS is supported, and can be run at the RTL- or gate-level (post
Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the ``USE_FSDB`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + FSDB (or VPD if the ``USE_VPD`` flag is set) and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
Power/Rail Analysis
^^^^^^^^^^^^^^^^^^^

8
vcs.mk
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@@ -1,10 +1,10 @@
HELP_COMPILATION_VARIABLES += \
" USE_FSDB = set to '1' to build VCS simulator to emit FSDB instead of VPD."
" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB."
HELP_SIMULATION_VARIABLES += \
" USE_FSDB = set to '1' to run VCS simulator emitting FSDB instead of VPD."
" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
ifdef USE_FSDB
ifndef USE_VPD
WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
else
WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
@@ -66,6 +66,6 @@ PREPROC_DEFINES = \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN
ifdef USE_FSDB
ifndef USE_VPD
PREPROC_DEFINES += +define+FSDB
endif

4
vlsi/Makefile
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@@ -177,7 +177,7 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifdef USE_FSDB
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
@@ -202,7 +202,7 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifdef USE_FSDB
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@