Merge pull request #650 from ucb-bar/make-help
Make help target and VCS/Verilator Cleanup
This commit is contained in:
Abraham Gonzalez
1
.gitignore
vendored
1
.gitignore
vendored
@@ -6,6 +6,7 @@ target
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*.stamp
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*.vcd
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*.swp
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*.swo
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*.log
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*#
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*~
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57
common.mk
57
common.mk
@@ -3,22 +3,45 @@
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#########################################################################################
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SHELL=/bin/bash
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ifndef RISCV
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$(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file)
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else
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$(info Running with RISCV=$(RISCV))
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endif
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#########################################################################################
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# specify user-interface variables
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#########################################################################################
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HELP_COMPILATION_VARIABLES += \
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" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \
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" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \
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" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \
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" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
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" EXTRA_SIM_REQS = additional make requirements to build the simulator"
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EXTRA_GENERATOR_REQS ?=
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EXTRA_SIM_CXXFLAGS ?=
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EXTRA_SIM_LDFLAGS ?=
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EXTRA_SIM_SOURCES ?=
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EXTRA_SIM_REQS ?=
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#----------------------------------------------------------------------------
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HELP_SIMULATION_VARIABLES += \
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" EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)"
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EXTRA_SIM_FLAGS ?=
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#----------------------------------------------------------------------------
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HELP_COMMANDS += \
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" run-binary = run [./$(shell basename $(sim))] and log instructions to file" \
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" run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \
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" run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
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" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" \
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" run-tests = run all assembly and benchmark tests"
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#########################################################################################
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# extra make variables/rules from subprojects
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#
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# EXTRA_GENERATOR_REQS - requirements needed for the main generator
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# EXTRA_SIM_FLAGS - runtime simulation flags
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# EXTRA_SIM_CC_FLAGS - cc flags for simulators
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# EXTRA_SIM_SOURCES - simulation sources needed for simulator
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# EXTRA_SIM_REQS - requirements to build the simulator
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# include additional subproject make fragments
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# see HELP_COMPILATION_VARIABLES
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#########################################################################################
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include $(base_dir)/generators/ariane/ariane.mk
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include $(base_dir)/generators/tracegen/tracegen.mk
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@@ -55,7 +78,6 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
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cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
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touch $@
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#########################################################################################
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# Bloop Project Definitions
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#########################################################################################
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@@ -140,18 +162,16 @@ verilog: $(sim_vsrcs)
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# helper rules to run simulations
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#########################################################################################
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.PHONY: run-binary run-binary-fast run-binary-debug run-fast
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# run normal binary with hardware-logged insn dissassembly
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run-binary: $(output_dir) $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
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#########################################################################################
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# helper rules to run simulator as fast as possible
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#########################################################################################
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# run simulator as fast as possible (no insn disassembly)
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run-binary-fast: $(output_dir) $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
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#########################################################################################
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# helper rules to run simulator with as much debug info as possible
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#########################################################################################
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# run simulator with as much debug info as possible
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run-binary-debug: $(output_dir) $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
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@@ -211,6 +231,13 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a
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$(dramsim_lib):
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$(MAKE) -C $(dramsim_dir) $(notdir $@)
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#########################################################################################
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# print help text
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#########################################################################################
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.PHONY: help
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help:
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@for line in $(HELP_LINES); do echo "$$line"; done
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#########################################################################################
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# Implicit rule handling
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#########################################################################################
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@@ -40,8 +40,7 @@ For a proprietry VCS simulation, enter the ``sims/vcs`` directory
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# Enter VCS directory
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cd sims/vcs
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.. _sim-default:
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.. _sw-sim-help:
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Simulating The Default Example
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-------------------------------
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@@ -82,6 +81,22 @@ For example:
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.. _sw-sim-custom:
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Makefile Variables and Commands
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-------------------------------
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You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``:
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.. code-block:: shell
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# Enter Verilator directory
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cd sims/verilator
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make help
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# Enter VCS directory
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cd sims/vcs
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make help
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.. _sim-default:
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Simulating A Custom Project
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-------------------------------
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@@ -166,4 +181,3 @@ An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourcefor
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For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
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If you have Synopsys licenses, we recommend using the DVE waveform viewer.
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@@ -41,16 +41,16 @@ include $(base_dir)/common.mk
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#########################################################################################
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VCS = vcs -full64
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VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES)
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VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
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#########################################################################################
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# vcs simulator rules
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#########################################################################################
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$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
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rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@
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$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \
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+define+DEBUG
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#########################################################################################
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@@ -61,8 +61,14 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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#########################################################################################
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# general cleanup rule
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# general cleanup rules
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#########################################################################################
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.PHONY: clean
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.PHONY: clean clean-sim clean-sim-debug
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clean:
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rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
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clean-sim:
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rm -rf csrc/ $(sim) ucli.key vc_hdrs.h
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clean-sim-debug:
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rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h
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@@ -22,7 +22,7 @@ include $(base_dir)/variables.mk
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sim_name = verilator
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#########################################################################################
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# vcs simulator types and rules
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# verilator simulator types and rules
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#########################################################################################
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sim_prefix = simulator
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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@@ -47,35 +47,49 @@ debug: $(sim_debug)
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include $(base_dir)/common.mk
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#########################################################################################
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# verilator binary and flags
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# verilator-specific user-interface variables and commands
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#########################################################################################
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HELP_COMPILATION_VARIABLES += \
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" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \
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" 'all' if full verilator runtime profiling" \
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" 'threads' if runtime thread profiling only" \
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" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build"
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#########################################################################################
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# verilator/cxx binary and flags
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#########################################################################################
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VERILATOR := verilator --cc --exe
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CXXFLAGS := \
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$(CXXFLAGS) -O1 -std=c++11 \
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-I$(RISCV)/include \
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-I$(dramsim_dir) \
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-D__STDC_FORMAT_MACROS \
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$(EXTRA_SIM_CC_FLAGS)
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#----------------------------------------------------------------------------------------
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# user configs
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#----------------------------------------------------------------------------------------
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VERILATOR_PROFILE ?= none
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RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,)
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RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
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--prof-threads --prof-cfuncs,\
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$(if $(filter $(VERILATOR_PROFILE),threads),\
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--prof-threads,))
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LDFLAGS := \
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$(LDFLAGS) \
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-L$(sim_dir) \
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-lpthread
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VERILATOR_FST_MODE ?= 0
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TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
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--trace,--trace-fst --trace-threads 1)
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TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
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VERILATOR_CC_OPTS = \
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#----------------------------------------------------------------------------------------
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# verilation configuration/optimization
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#----------------------------------------------------------------------------------------
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# we initially had --noassert for performance, but several modules use
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# assertions, including dramsim, so we enable --assert by default
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VERILATOR_OPT_FLAGS := \
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-O3 \
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-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
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-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
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-LDFLAGS "$(LDFLAGS)" \
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$(RISCV)/lib/libfesvr.a \
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$(dramsim_lib)
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--x-assign fast \
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--x-initial fast \
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--output-split 10000 \
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--output-split-cfuncs 100
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# default flags added for ariane
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ARIANE_VERILATOR_FLAGS = \
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# default flags added for external IP (ariane/NVDLA)
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VERILOG_IP_VERILATOR_FLAGS := \
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--unroll-count 256 \
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-Werror-PINMISSING \
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-Werror-IMPLICIT \
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-Wno-PINCONNECTEMPTY \
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-Wno-ASSIGNDLY \
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-Wno-DECLFILENAME \
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@@ -85,29 +99,82 @@ ARIANE_VERILATOR_FLAGS = \
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-Wno-style \
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-Wall
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# normal flags used for chipyard builds (that are incompatible with ariane)
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CHIPYARD_VERILATOR_FLAGS = \
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# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
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CHIPYARD_VERILATOR_FLAGS := \
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--assert
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# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
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# NOTE: defer the evaluation of this until it is used!
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PLATFORM_OPTS = $(shell \
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if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
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then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
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else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
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# Use --timescale to approximate timescale behavior of pre-4.034
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TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
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VERILATOR_NONCC_OPTS = \
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$(TIMESCALE_OPTS) \
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--top-module $(VLOG_MODEL) \
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--vpi \
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-Wno-fatal \
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$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
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--output-split 10000 \
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--output-split-cfuncs 100 \
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--max-num-width 1048576 \
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-f $(sim_common_files) \
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$(sim_vsrcs)
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|
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VERILATOR_DEFINES = \
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# see: https://github.com/ucb-bar/riscv-mini/issues/31
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||||
MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
|
||||
|
||||
PREPROC_DEFINES := \
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||||
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
|
||||
+define+STOP_COND=\$$c\(\"done_reset\"\)
|
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|
||||
VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES)
|
||||
VERILATOR_NONCC_OPTS = \
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$(RUNTIME_PROFILING_VFLAGS) \
|
||||
$(VERILATOR_OPT_FLAGS) \
|
||||
$(PLATFORM_OPTS) \
|
||||
-Wno-fatal \
|
||||
$(TIMESCALE_OPTS) \
|
||||
$(MAX_WIDTH_OPTS) \
|
||||
$(PREPROC_DEFINES) \
|
||||
--top-module $(VLOG_MODEL) \
|
||||
--vpi \
|
||||
-f $(sim_common_files) \
|
||||
$(sim_vsrcs)
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
# gcc configuration/optimization
|
||||
#----------------------------------------------------------------------------------------
|
||||
# -flto slows down compilation on small-memory and breaks on firesim-manager
|
||||
CXX_OPT_FLAGS := -O3
|
||||
|
||||
VERILATOR_CXXFLAGS = \
|
||||
$(CXXFLAGS) \
|
||||
$(RUNTIME_PROFILING_CFLAGS) \
|
||||
$(TRACING_CFLAGS) \
|
||||
$(CXX_OPT_FLAGS) \
|
||||
-std=c++11 \
|
||||
-D__STDC_FORMAT_MACROS \
|
||||
-DTEST_HARNESS=V$(VLOG_MODEL) \
|
||||
-DVERILATOR \
|
||||
-I$(RISCV)/include \
|
||||
-I$(dramsim_dir) \
|
||||
-I$(build_dir) \
|
||||
-include $(build_dir)/$(long_name).plusArgs \
|
||||
-include $(build_dir)/verilator.h \
|
||||
$(EXTRA_SIM_CXXFLAGS)
|
||||
|
||||
VERILATOR_LDFLAGS = \
|
||||
$(LDFLAGS) \
|
||||
$(RUNTIME_PROFILING_CFLAGS) \
|
||||
-L$(RISCV)/lib \
|
||||
-Wl,-rpath,$(RISCV)/lib \
|
||||
-L$(sim_dir) \
|
||||
-L$(dramsim_dir) \
|
||||
-lfesvr \
|
||||
-lpthread \
|
||||
-ldramsim \
|
||||
$(EXTRA_SIM_LDFLAGS)
|
||||
|
||||
VERILATOR_CC_OPTS = \
|
||||
-CFLAGS "$(VERILATOR_CXXFLAGS)" \
|
||||
-LDFLAGS "$(VERILATOR_LDFLAGS)"
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
# full verilator+gcc opts
|
||||
#----------------------------------------------------------------------------------------
|
||||
VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
|
||||
|
||||
#########################################################################################
|
||||
# verilator build paths and file names
|
||||
@@ -127,13 +194,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
|
||||
$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
|
||||
rm -rf $(model_dir)
|
||||
mkdir -p $(model_dir)
|
||||
$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
|
||||
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
|
||||
touch $@
|
||||
|
||||
$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
|
||||
rm -rf $(model_dir_debug)
|
||||
mkdir -p $(model_dir_debug)
|
||||
$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
|
||||
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
|
||||
touch $@
|
||||
|
||||
#########################################################################################
|
||||
@@ -155,8 +222,14 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
|
||||
(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
|
||||
|
||||
#########################################################################################
|
||||
# general cleanup rule
|
||||
# general cleanup rules
|
||||
#########################################################################################
|
||||
.PHONY: clean
|
||||
.PHONY: clean clean-sim clean-sim-debug
|
||||
clean:
|
||||
rm -rf $(gen_dir) $(sim_prefix)-*
|
||||
|
||||
clean-sim:
|
||||
rm -rf $(model_dir) $(sim)
|
||||
|
||||
clean-sim-debug:
|
||||
rm -rf $(model_dir_debug) $(sim_debug)
|
||||
|
||||
@@ -49,7 +49,7 @@ ifdef ENABLE_DROMAJO
|
||||
EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS)
|
||||
|
||||
# CC flags needed for all simulations
|
||||
EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR)
|
||||
EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR)
|
||||
|
||||
# sourced needed for simulation
|
||||
EXTRA_SIM_SOURCES += $(DROMAJO_LIB)
|
||||
|
||||
62
variables.mk
62
variables.mk
@@ -1,23 +1,51 @@
|
||||
#########################################################################################
|
||||
# makefile variables shared across multiple makefiles
|
||||
# - to use the help text, your Makefile should have a 'help' target that just
|
||||
# prints all the HELP_LINES
|
||||
#########################################################################################
|
||||
HELP_COMPILATION_VARIABLES =
|
||||
HELP_PROJECT_VARIABLES = \
|
||||
" SUB_PROJECT = use the specific subproject default variables [$(SUB_PROJECT)]" \
|
||||
" SBT_PROJECT = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \
|
||||
" MODEL = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \
|
||||
" VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \
|
||||
" MODEL_PACKAGE = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \
|
||||
" CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \
|
||||
" CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \
|
||||
" GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \
|
||||
" TB = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \
|
||||
" TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]"
|
||||
|
||||
#########################################################################################
|
||||
# variables to invoke the generator
|
||||
# descriptions:
|
||||
# SBT_PROJECT = the SBT project that you should find the classes/packages in
|
||||
# MODEL = the top level module of the project in Chisel (normally the harness)
|
||||
# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
|
||||
# MODEL_PACKAGE = the scala package to find the MODEL in
|
||||
# CONFIG = the configuration class to give the parameters for the project
|
||||
# CONFIG_PACKAGE = the scala package to find the CONFIG class
|
||||
# GENERATOR_PACKAGE = the scala package to find the Generator class in
|
||||
# TB = wrapper over the TestHarness needed to simulate in a verilog simulator
|
||||
# TOP = top level module of the project (normally the module instantiated by the harness)
|
||||
#
|
||||
# project specific:
|
||||
# SUB_PROJECT = use the specific subproject default variables
|
||||
#########################################################################################
|
||||
HELP_SIMULATION_VARIABLES = \
|
||||
" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
|
||||
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]"
|
||||
|
||||
# include default simulation rules
|
||||
HELP_COMMANDS = \
|
||||
" help = display this help" \
|
||||
" default = compiles non-debug simulator [./$(shell basename $(sim))]" \
|
||||
" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \
|
||||
" clean = remove all debug/non-debug simulators and intermediate files" \
|
||||
" clean-sim = removes non-debug simulator and simulator-generated files" \
|
||||
" clean-sim-debug = removes debug simulator and simulator-generated files"
|
||||
|
||||
HELP_LINES = "" \
|
||||
" design specifier variables:" \
|
||||
" ---------------------------" \
|
||||
$(HELP_PROJECT_VARIABLES) \
|
||||
"" \
|
||||
" compilation variables:" \
|
||||
" ----------------------" \
|
||||
$(HELP_COMPILATION_VARIABLES) \
|
||||
"" \
|
||||
" simulation variables:" \
|
||||
" ---------------------" \
|
||||
$(HELP_SIMULATION_VARIABLES) \
|
||||
"" \
|
||||
" some useful general commands:" \
|
||||
" -----------------------------" \
|
||||
$(HELP_COMMANDS) \
|
||||
""
|
||||
|
||||
#########################################################################################
|
||||
# subproject overrides
|
||||
@@ -140,7 +168,7 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
|
||||
# 1) the sed removes a leading {file:<path>} that sometimes needs to be
|
||||
# provided to SBT when a project but not for bloop.
|
||||
# 2) Generally, one could could pass '--' to indicate all remaining arguments are
|
||||
# destined for the scala Main, however a bug in Bloop's argument parsing causes the
|
||||
# destined for the scala Main, however a bug in Bloop's argument parsing causes the
|
||||
# --nailgun-port argument to be lost in this case. Workaround this by prefixing
|
||||
# every main-destined argument with "--args"
|
||||
define run_scala_main
|
||||
|
||||
41
vcs.mk
41
vcs.mk
@@ -11,15 +11,38 @@ endif
|
||||
CLOCK_PERIOD ?= 1.0
|
||||
RESET_DELAY ?= 777.7
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
# gcc configuration/optimization
|
||||
#----------------------------------------------------------------------------------------
|
||||
CXX_OPT_FLAGS := -O3
|
||||
|
||||
VCS_CXXFLAGS = \
|
||||
$(CXXFLAGS) \
|
||||
$(CXX_OPT_FLAGS) \
|
||||
-I$(RISCV)/include \
|
||||
-I$(dramsim_dir) \
|
||||
-std=c++11 \
|
||||
$(EXTRA_SIM_CXXFLAGS)
|
||||
|
||||
VCS_LDFLAGS = \
|
||||
$(LDFLAGS) \
|
||||
-L$(RISCV)/lib \
|
||||
-Wl,-rpath,$(RISCV)/lib \
|
||||
-L$(sim_dir) \
|
||||
-L$(dramsim_dir) \
|
||||
-lfesvr \
|
||||
-ldramsim \
|
||||
$(EXTRA_SIM_LDFLAGS)
|
||||
|
||||
# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
|
||||
VCS_CC_OPTS = \
|
||||
-CC "-I$(RISCV)/include" \
|
||||
-CC "-I$(dramsim_dir)" \
|
||||
-CC "-std=c++11" \
|
||||
-CC "$(EXTRA_SIM_CC_FLAGS)"
|
||||
-CFLAGS "$(VCS_CXXFLAGS)" \
|
||||
-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
|
||||
$(filter -l%,$(VCS_LDFLAGS))
|
||||
|
||||
VCS_NONCC_OPTS = \
|
||||
$(dramsim_lib) \
|
||||
$(RISCV)/lib/libfesvr.a \
|
||||
-notice \
|
||||
-line \
|
||||
+lint=all,noVCDE,noONGS,noUI \
|
||||
-error=PCWM-L \
|
||||
-error=noZMMCM \
|
||||
@@ -27,7 +50,6 @@ VCS_NONCC_OPTS = \
|
||||
-quiet \
|
||||
-q \
|
||||
+rad \
|
||||
+v2k \
|
||||
+vcs+lic+wait \
|
||||
+vc+list \
|
||||
-f $(sim_common_files) \
|
||||
@@ -35,10 +57,9 @@ VCS_NONCC_OPTS = \
|
||||
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
|
||||
-debug_pp \
|
||||
+incdir+$(build_dir) \
|
||||
$(sim_vsrcs) \
|
||||
+libext+.v
|
||||
$(sim_vsrcs)
|
||||
|
||||
VCS_DEFINE_OPTS = \
|
||||
PREPROC_DEFINES = \
|
||||
+define+VCS \
|
||||
+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
|
||||
+define+RESET_DELAY=$(RESET_DELAY) \
|
||||
|
||||
@@ -115,15 +115,20 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file
|
||||
done
|
||||
echo " options_meta: 'append'" >> $@
|
||||
echo " defines:" >> $@
|
||||
for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \
|
||||
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " defines_meta: 'append'" >> $@
|
||||
echo " compiler_opts:" >> $@
|
||||
for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \
|
||||
echo " compiler_cc_opts:" >> $@
|
||||
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " compiler_opts_meta: 'append'" >> $@
|
||||
echo " compiler_cc_opts_meta: 'append'" >> $@
|
||||
echo " compiler_ld_opts:" >> $@
|
||||
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " compiler_ld_opts_meta: 'append'" >> $@
|
||||
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
|
||||
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
|
||||
echo " execution_flags:" >> $@
|
||||
|
||||
Submodule vlsi/hammer updated: cbc907dfe8...bed4d34094
Submodule vlsi/hammer-synopsys-plugins updated: e5ec0da8ad...f8a7922220
Reference in New Issue
Block a user