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Author SHA1 Message Date
abejgonzalez
eb44ae13d4 makefile changes/split | add scripts 2019-04-15 10:17:41 -07:00
alonamid
31e30b2ec7 change dir structure 2019-04-15 10:17:41 -07:00
John Wright
5be8de1288 Build additional annos and fir (#64) 2019-03-29 14:00:52 -07:00
John Wright
e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin Schmidt
3425def36b Bumps barstools and fixes build system after (#63) 
Barstools now handles annotations correctly.
This means that the blackboxresources for the harness
and top are different and need to be merged in the build system.
We also add all Sim*.cc files to default resources as our new emulator
demands. We then remove them from the harness .f file to avoid having
to detect which ones to include selectively.
 2019-03-28 11:47:32 -07:00
Colin Schmidt
cf9136de4a backport ucb-bar/project-template/pull/59 2019-03-28 09:36:16 -07:00
Colin Schmidt
8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidt
affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Colin Schmidt
fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00
Abraham Gonzalez
817726ff1f stop exceptions on empty conf files (#43) 
* stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
 2019-03-18 10:15:50 -07:00
Colin Schmidt
de94c2376a Add Travis (#48) 2019-03-18 10:07:10 -07:00
alonamid
419d41239f Merge pull request #59 from ucb-bar/rebar-srams-fix 
Bump barstools and re-add infer-rw for better SRAM mapping
 2019-03-18 09:30:01 -07:00
Colin Schmidt
f5b452229a Avoid using the github redirect for mdf 2019-03-18 09:25:59 -07:00
Colin Schmidt
ffee1f1e98 Bump barstools and re-add infer-rw for better SRAM mapping 2019-03-18 07:31:27 -07:00
Colin Schmidt
0b9d74ada7 Fix unit tests update cost function once more 
bump mdf to master
 2019-03-18 07:25:04 -07:00
Colin Schmidt
44e97826d4 Fix cost metric for non Compiler libs 
Also a small fix from reviewer
 2019-03-18 07:25:04 -07:00
Colin Schmidt
6cdf978a6d Fix forms of passes to happen before replseqmem 
This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
 2019-03-18 07:25:04 -07:00
Colin Schmidt
98a410812c Filter compiler libraries before mapping 
The filter is always by family and maskability and then by any
integral mappings.
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a0510e6664 Change cost to double from BigInt and fix default metric 
I don't think it was adding anything and now we can get rid of
the weird +1/-1
 2019-03-18 07:25:04 -07:00
Colin Schmidt
45278a6de0 Make SRAM per port clocks optional 
Connects to whatever clock ports are available
 2019-03-18 07:25:04 -07:00
alonamid
319d2fedf7 more docs 2019-03-16 00:15:02 -07:00
Abraham Gonzalez
87f9c14dcc Merge pull request #54 from ucb-bar/misc-changes 
Makefile + Ctags
 2019-03-15 18:47:00 -07:00
abejgonzalez
e33f2fcedf find now follows symlinks 2019-03-12 15:39:19 -07:00
abejgonzalez
c364869563 default to .gitignoring all files in verisim/vsim | read verilator.mk 2019-03-12 14:39:15 -07:00
abejgonzalez
4fd1bfbd56 delete .ctags (have the user put this in their home) 2019-03-12 14:39:15 -07:00
abejgonzalez
2c246af110 rename makefiles | move verilog rule to common.mk 2019-03-12 14:39:15 -07:00
abejgonzalez
82273107c1 makefile changes/split | add scripts 2019-03-12 14:39:15 -07:00
alonamid
49ab106b9e docs placeholder 2019-03-12 14:30:38 -07:00
alonamid
6ccb3defc1 add toolchains 2019-03-12 14:30:38 -07:00
alonamid
4d62a2b215 docs placeholder 2019-03-12 14:30:38 -07:00
alonamid
2e7791a57d add chisel and firrtl submodules 2019-03-12 14:30:38 -07:00
alonamid
2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Colin Schmidt
17c38a502a Help people who want to run tests (#50) 
* Help people who want to run tests

* Include generated makefrags for simulation
 2019-03-11 11:26:27 -07:00
Paul Rigge
0b7f7b43bc Merge pull request #52 from ucb-bar/fixAXI 
Fix AXI4 example.
 2019-03-07 20:59:05 -08:00
Paul Rigge
61d1798888 Fix AXI4 example. 
I accidentally stumbled into a working AXI4 configuration by multiplying
pbus.beatBytes by 8, but it was fragile. This is the "right way" to add
an AXI4 peripheral.
 2019-03-07 20:58:23 -08:00
Paul Rigge
bf23d7aa6c Fix VCS build. 
VCS doesn't use the same arguments for C headers that verilator uses.
Generate the dot-f file differently for the different simulators.
 2019-03-06 23:06:24 -08:00
Paul Rigge
467fdd06e9 Bump to testchipip from a dev branch to master 2019-03-06 23:03:33 -08:00
Paul Rigge
8a522ba404 Fix some build system problems. 
1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
 2019-03-06 22:10:31 -08:00
Paul Rigge
c7d56c09a0 Bump testchipip to master 2019-03-06 21:15:14 -08:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47) 
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
 2019-03-06 18:22:21 -08:00
Colin Schmidt
a10a6cca35 Add SimDTM to list of extmodules 2019-03-01 18:52:41 -08:00
Howard Mao
e5cbf49bb4 fix README documentation for RoCC accelerators 2019-02-27 14:10:00 -08:00
Paul Rigge
51ca3dd1b9 Merge pull request #49 from ucb-bar/fix-verisim-debug 
Debug simulator still needs all vsrcs
 2019-02-26 13:34:31 -08:00
Colin Schmidt
358e6ad49d Debug simulator still needs all vsrcs 2019-02-26 13:08:13 -08:00
Paul Rigge
cd71e3232e Merge pull request #46 from ucb-bar/updateGitmodules 
Update gitmodule url to use https
 2019-02-19 10:49:44 -08:00
Paul Rigge
0de9d396b4 Update gitmodule url to use https 
The .git suffix was dropped and git@ was used instead of https://

Update to be consistent with other submodules.
 2019-02-19 10:48:23 -08:00
John Wright
d97afcdfbc Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a 
bug using verilator, make the whitespace consistend in
Makefrag-verilator, explicitly name the verilog sources to match vsim,
and update verisim/Makefile to use the new source variable names
 2019-02-13 21:13:08 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the 
memories as external modules, which makes VLSI flows easier to plug in.
 2019-02-13 21:13:08 -08:00
James Dunn
9d505d6063 Fixed index offset in mask port mapping. (#38) 
Fixed index offset in mask port mapping.
 2019-02-13 15:17:12 -08:00
John Wright
1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00