Nayiri
|
3a6677bc30
|
Fix clock name and macro paths for Sky130 VLSI flow (#1882)
|
2024-05-19 17:54:47 -07:00 |
|
Nayiri
|
42622919cd
|
fixing macro paths for yosys with circt generated verilog [skip ci]
|
2023-12-14 18:02:32 -08:00 |
|
abejgonzalez
|
088e9ea45a
|
Remove references to ENABLE_YOSYS
|
2023-12-13 10:07:14 -08:00 |
|
abejgonzalez
|
c7f1fe220d
|
Enable precommit | Format files
|
2023-08-28 14:56:55 -07:00 |
|
Nayiri K
|
222059941e
|
renamed clock_clock to clock_uncore_clock
|
2023-06-30 15:04:38 -07:00 |
|
Nayiri Krzysztofowicz
|
dd7e221a45
|
changing tutorial VLSI_TOP to RocketTile to save time
|
2023-03-12 19:04:14 -07:00 |
|
Nayiri K
|
0f326ae980
|
floorplan for openroad flow is different from commercial flow bc of srams
|
2023-03-10 23:18:20 -08:00 |
|
Nayiri K
|
6dba66f56c
|
updated tutorial configuration files [skip ci]
|
2023-03-10 15:19:47 -08:00 |
|
abejgonzalez
|
292cc753ce
|
Run pre-commit on all files
|
2022-12-21 15:59:46 -08:00 |
|
Nayiri K
|
6418afc095
|
re-added macro placement
|
2022-09-28 18:58:42 -07:00 |
|
Nayiri K
|
ad3188bca2
|
improved example-designs override
|
2022-09-28 17:06:53 -07:00 |
|
Nayiri K
|
49479754d3
|
minor tweaks
|
2022-09-27 14:04:54 -07:00 |
|
Nayiri K
|
fbd5966d14
|
refactored some yaml design files for the openroad tutorial
|
2022-09-27 12:05:58 -07:00 |
|