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47 Commits

Author SHA1 Message Date
Jerry Zhao
63c46d89c1 Bump sifive-blocks 2020-05-05 13:58:01 -07:00
Abraham Gonzalez
02367022b0 Fix "WithHeterCoresSetup" in hetero. docs (#537) 2020-04-29 16:25:02 -07:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480) 
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
 2020-04-01 14:03:56 -07:00
Howard Mao
2528708c15 add documentation on ring network and system bus 2020-03-19 10:13:03 -07:00
Howard Mao
ffb9c81ce2 fix literalincludes and other path references in documentation 2020-03-16 12:06:59 -07:00
alonamid
d5592ca1a7 bump firesim (#470) 
* Fix capitalization in docs (#419)

* Update Quick-Start.rst

* [ci skip] Fix Typos (#444)

* Update Quick-Start.rst

* bump firesim

Co-authored-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
 2020-03-13 18:44:47 -07:00
Abraham Gonzalez
01238c8b7a Rename Config Mixins to Fragments (#451) 
* [docs] rename config mixins -> fragments [ci skip]

* [docs] cleanup naming | link similar sections [ci skip]

* [boom] bump for mixin rename [ci skip]

* [docs] cleanup capitalization [ci skip]

* [docs] consistent config fragment naming [ci skip]

* [boom] bump boom for documentation changes [ci skip]

* [docs] update source comments [ci skip]

* [docs] fix last config fragment name [ci skip]

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
 2020-02-27 09:31:08 -08:00
Jerry Zhao
708a5fb9a6 Address generator unification PR reviews 2020-02-23 22:53:14 -08:00
Jerry Zhao
c12819eb52 Update docs 2020-02-13 12:33:28 -08:00
Abraham Gonzalez
1859054f73 [docs] update documentation [ci skip] (#393) 2020-01-23 13:36:21 -08:00
Jerry Zhao
ac5235e5ed Revamp the config system for Top/Harness (#347) 
* Refactor how Configs parameterize the Top and TestHarnesses

* Bump sha3, testchipip, icenet, firesim
 2020-01-21 20:44:54 -08:00
Baltazar Ortiz
d277984eab Update scratchpad config (#371) 
* Update scratchpad config

Previous version didn't compile as per
https://github.com/ucb-bar/chipyard/issues/365

* Update docs/Customization/Memory-Hierarchy.rst

Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>

* Fix indentation

* Update memory hierarchy doc for PR

Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2020-01-10 12:02:21 -07:00
alonamid
4853300de6 Merge pull request #247 from ucb-bar/firrtl-docs 
Firrtl Transforms Documentation
 2019-09-27 00:45:44 -07:00
abejgonzalez
f24eba30f6 change order of dontTouch | make more concise [ci skip] 2019-09-27 00:32:47 -07:00
abejgonzalez
802c11dbef add some extra clarity [ci skip] 2019-09-26 23:16:57 -07:00
abejgonzalez
c6bdeda9ed small fixes + cleaner example explanation [ci skip] 2019-09-26 23:10:51 -07:00
Albert Magyar
f2939823ce Clean up paragraph on FIRRTL transform BlackBox support 2019-09-26 10:09:02 -07:00
Albert Magyar
28664ea8df Update section header on Verilog support in chipyard tools 2019-09-26 09:50:41 -07:00
Albert Magyar
216ae3ee54 Add more tips for Verilog blackbox integration 2019-09-26 09:32:38 -07:00
Albert Magyar
c2ce173195 Add Verilog MMIO GCD peripheral example 2019-09-26 01:47:31 -07:00
abejgonzalez
71db99911b extra cleanup [ci skip] 2019-09-25 17:54:47 -07:00
abejgonzalez
e90d53e31e add tranforms to index [ci skip] 2019-09-25 13:21:11 -07:00
abejgonzalez
9199a02e1e add literal references | cleanup firrtl-transform-docs [ci skip] 2019-09-25 13:21:01 -07:00
alonamid
eae7645159 sifive generators 2019-09-25 11:56:26 -07:00
abejgonzalez
4c443d2077 start firrtl transform docs [skip ci] 2019-09-25 10:26:40 -07:00
abejgonzalez
fd6d3272e4 add quotes around core/tile [skip ci] 2019-09-20 18:00:11 -07:00
abejgonzalez
898f0fd2d4 cleanup grammar a bit [skip ci] 2019-09-20 17:51:46 -07:00
abejgonzalez
ff992ef24e add hart of 2 to heter explanation | footnote about tile v core [skip ci] 2019-09-20 17:36:53 -07:00
abejgonzalez
edaf99ca9a small clarifications + cleanup [skip ci] 2019-09-20 12:25:23 -07:00
Howard Mao
d5bccc0455 add additional example code as literalincludes 2019-09-12 18:08:45 -07:00
Howard Mao
6ae60b94c6 correct capitalization in Adding an Accelerator/Device 2019-09-12 17:56:12 -07:00
Howard Mao
9a8d6c908f fix verilator invocation in Adding an Accelerator 2019-09-12 17:54:08 -07:00
Howard Mao
bc903b8407 more on customization of L1 2019-09-12 14:34:57 -07:00
Howard Mao
c6f6b2e117 mention address of BootROM and first instruction 2019-09-11 12:13:08 -07:00
Howard Mao
200fec07e6 make purpose of CachelessRocketConfig clearer 2019-09-11 12:13:08 -07:00
Howard Mao
9bb4215c7d add changes Alon requested 2019-09-11 12:13:08 -07:00
Howard Mao
646d7cba4c use literalinclude directive to pull source directly from example package 2019-09-11 12:13:08 -07:00
Howard Mao
a4371fa917 add section on SoC boot process 2019-09-11 12:13:08 -07:00
Howard Mao
c0f49a47d8 more fixes to Adding an Accelerator 2019-09-11 12:13:08 -07:00
Howard Mao
d411dd9a6c fill out Memory Hierarchy section 2019-09-11 12:13:08 -07:00
Howard Mao
b748dcf14e update 'Adding an Accelerator' for API changes 2019-09-11 12:13:08 -07:00
Howard Mao
ab888d32a7 Merge pull request #215 from ucb-bar/dev-tracegen 
Add TraceGen project
 2019-08-31 05:21:51 +08:00
Howard Mao
c33c6a2985 get rid of now-defunct documention 2019-08-30 11:38:08 -07:00
Jerry Zhao
4de40d3863 Update naming in docs 2019-08-28 14:53:24 -07:00
abejgonzalez
8ba73d13b8 fix the doc warnings 2019-08-08 17:19:10 -07:00
abejgonzalez
2e043bd06f Merge remote-tracking branch 'origin/dev' into abe-docs-dev 2019-08-07 23:39:11 -07:00
alonamid
aec0fb73c4 docs reorg 2019-07-25 01:20:38 -07:00