5 Commits

Author	SHA1	Message	Date
Nayiri	42622919cd	fixing macro paths for yosys with circt generated verilog [skip ci]	2023-12-14 18:02:32 -08:00
abejgonzalez	088e9ea45a	Remove references to ENABLE_YOSYS	2023-12-13 10:07:14 -08:00
abejgonzalez	c7f1fe220d	Enable precommit | Format files	2023-08-28 14:56:55 -07:00
Nayiri K	222059941e	renamed clock_clock to clock_uncore_clock	2023-06-30 15:04:38 -07:00
Nayiri Krzysztofowicz	dd7e221a45	changing tutorial VLSI_TOP to RocketTile to save time	2023-03-12 19:04:14 -07:00