Commit Graph

114 Commits

Author SHA1 Message Date
Abraham Gonzalez
45f63a1409 Merge pull request #879 from ucb-bar/remove-gen-sim-files
Remove GenerateSimFiles and use make instead
2021-05-13 16:41:17 -05:00
abejgonzalez
a0de9a0cfb Depend on build_dir 2021-05-06 20:36:28 -07:00
abejgonzalez
aa4eff3407 Add small comments about thin client 2021-05-06 14:08:47 -07:00
abejgonzalez
7195c0cbd1 Check for thin client flag | Bump SBT to 1.4.9 2021-05-06 14:05:59 -07:00
abejgonzalez
365e2ea81e Fix BINARY check 2021-05-06 01:11:30 -07:00
abejgonzalez
f9957b2ce3 Check for BINARY flag when doing run-* 2021-05-06 00:56:14 -07:00
abejgonzalez
1d52899736 Remove GenerateSimFiles and use make instead 2021-05-06 00:27:11 -07:00
Tynan McAuley
7d32e6c0b2 make: Use 'fd' over 'find' if possible 2021-04-22 15:27:05 -07:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
abejgonzalez
939e3a9f94 Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools 2020-12-11 14:18:18 -08:00
abejgonzalez
714687c962 Add to help target | Cleanup build.sbt a bit more 2020-12-04 14:18:51 -08:00
abejgonzalez
d0079a9659 Cleanup helper sbt targets | Use project/target/active.json for SBT timestamp 2020-12-03 14:24:04 -08:00
abejgonzalez
a0e2dcfc4e Remove support for bloop 2020-12-02 14:46:46 -08:00
abejgonzalez
4e53dc1e66 Cleanly reload proj. defs. with thin client support 2020-12-02 12:18:12 -08:00
abejgonzalez
5bc7e6cd68 Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS 2020-12-01 22:28:23 -08:00
abejgonzalez
6f827456c8 Helper make target to launch SBT | Move SBT_OPTS to SBT variable 2020-11-20 16:09:07 -08:00
abejgonzalez
70d43210d8 [temp] Unable to build/get past chisel-testers 2020-11-15 18:18:04 -08:00
abejgonzalez
3994bcecdf Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support 2020-11-05 11:08:36 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
Abraham Gonzalez
a07369acaf Merge remote-tracking branch 'ch/lazy-iobinders' into local-fpga-temp 2020-10-20 21:23:11 -07:00
Alon Amid
4a317b0cab differentiate default config package delimiter 2020-10-15 17:07:20 +00:00
abejgonzalez
341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp 2020-10-13 16:23:41 -07:00
dunn
309b9ee7ae Merge remote-tracking branch 'upstream/dev' into local-fpga-arty-abe 2020-10-06 12:23:18 -07:00
dunn
9664b848e9 Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src. 2020-10-06 11:20:27 -07:00
abejgonzalez
a8083aa570 First pass at fpga-shells with IOBinders 2020-09-07 11:48:27 -07:00
Jerry Zhao
23e4c22a44 Don't run find in base_dir to avoid slow filesystem search 2020-09-02 23:52:55 -07:00
abejgonzalez
425b8ce850 Add support for multi-threaded verilator 2020-08-20 23:37:17 -07:00
Abraham Gonzalez
af61c533da Merge .PHONY variables 2020-08-19 22:15:55 -07:00
Abraham Gonzalez
b7d9472b4a Cleanup help commands 2020-08-19 22:10:18 -07:00
Abraham Gonzalez
3b991f3ed7 Move vcs flags to vcs.mk | Misc. cleanup 2020-08-18 11:14:01 -07:00
Abraham Gonzalez
b007d79820 Add help section to makefiles + Reorganize 2020-08-17 20:28:05 -07:00
Colin Schmidt
edbb86ef98 Move elf2hex preprocessing into separate script 2020-08-05 11:23:48 -07:00
Colin Schmidt
93c7fef942 We need to uppercase hex chars for bc 2020-08-05 10:03:21 -07:00
Jerry Zhao
b719919934 Add RANDOM_SEED variable to set random init for VCS and Verilator simulations 2020-07-20 18:25:18 -07:00
Jerry Zhao
2196a621c6 Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness 2020-07-09 12:39:17 -07:00
David Biancolin
863e68ff30 Merge pull request #576 from ucb-bar/make-suffix-rules
Disable all make suffix rules for improved EC2 performance
2020-06-27 13:37:16 -07:00
David Biancolin
f311aa37d1 [make] Remove unneeded CLASSES variables 2020-06-21 23:44:01 +00:00
David Biancolin
c5b09541be [make] Find all build.sbt files and use them for bloop prereqs 2020-06-21 23:36:23 +00:00
David Biancolin
ce67134329 Support using bloop instead of SBT 2020-06-21 23:25:53 +00:00
Jerry Zhao
71f340a0af Use output_dir for run-binary logs and waveforms (#596)
* Dump run-binary files in output/$(long_name) instead of current directory
* Remove run-none rules, these were equivalent to run-binary BINARY=none
2020-06-12 10:08:55 -07:00
Jerry Zhao
623bafacd5 Warn if RISCV unset (#601) 2020-06-10 14:46:53 -07:00
David Biancolin
48ba92dff1 Disable all make suffix rules for improved EC2 performance 2020-05-28 12:36:17 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
David Biancolin
ebe993cefe Assemble the firrt-test.jar and put it in its own directory 2020-05-14 19:25:21 +00:00
David Biancolin
2fa9a41902 [make] Fix firrtl prerequiste lookup 2020-05-11 03:46:03 +00:00
Howard Mao
a905dbedcc add make rules for running simulator without executable 2020-04-28 10:32:28 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00
Abraham Gonzalez
3d253c0f67 [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder
2020-03-30 17:04:45 -07:00