Commit Graph

85 Commits

Author SHA1 Message Date
abejgonzalez
7a0ca12f59 Bump build.sbt 2020-12-27 21:27:01 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
Tim Snyder
f693972e12 Start RC bump
Bump to pre-merge chipsalliance/rocket-chip#2764 to get it
going while picking up the chisel/firrtl bugfixes in 3/1.4.1+
2020-12-18 18:00:21 +00:00
abejgonzalez
a8d6daef93 Small build.sbt comments 2020-12-13 09:32:44 -08:00
abejgonzalez
939e3a9f94 Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools 2020-12-11 14:18:18 -08:00
abejgonzalez
714687c962 Add to help target | Cleanup build.sbt a bit more 2020-12-04 14:18:51 -08:00
abejgonzalez
70fa0a037d Print full stack traces (default traceLevel = 0) | Bump FireSim 2020-12-03 14:57:05 -08:00
abejgonzalez
f1df2ec69e Bump FireSim/Hwacha | Cleanup linting 2020-12-03 12:51:24 -08:00
abejgonzalez
5bc7e6cd68 Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS 2020-12-01 22:28:23 -08:00
abejgonzalez
b7ed614b19 Attempt at "fixing" build.sbt | Bump sub-projects 2020-11-30 21:22:55 -08:00
abejgonzalez
9545abb65d Working elaboration (breaks during barstools FIRRTL) 2020-11-21 16:18:02 -08:00
abejgonzalez
3dfc03c31d Add more plugins and libdeps 2020-11-20 17:02:59 -08:00
abejgonzalez
c6e49e0716 Follow RC's SBT sriracha use | Bump FIRRTL plugin 2020-11-20 15:05:00 -08:00
abejgonzalez
51b254f6b3 Small build.sbt cleanup 2020-11-20 13:52:38 -08:00
abejgonzalez
2b4fb555af Use ProjectRef for FIRRTL and use it for firrtl-interpreter 2020-11-20 12:15:19 -08:00
abejgonzalez
11ab0d7346 Put libdeps back into commonSettings in build.sbt 2020-11-20 10:48:44 -08:00
abejgonzalez
571e7517eb Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral 2020-11-19 20:06:28 -08:00
abejgonzalez
a0d479f3ea Working FIRRTL/RC/Chisel3 build | chisel-testers still broken 2020-11-16 22:55:04 -08:00
abejgonzalez
9d9813fe0a [temp] Following RC's way to build Chisel from source or Maven [ci skip] 2020-11-16 22:24:29 -08:00
abejgonzalez
70d43210d8 [temp] Unable to build/get past chisel-testers 2020-11-15 18:18:04 -08:00
abejgonzalez
999ae05bfe Address some docs, build.sbt, .gitmodules 2020-11-12 15:31:34 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
abejgonzalez
341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp 2020-10-13 16:23:41 -07:00
abejgonzalez
56eead4053 NOT WORKING: VCU118 Commit 2020-09-08 17:04:56 -07:00
abejgonzalez
a8083aa570 First pass at fpga-shells with IOBinders 2020-09-07 11:48:27 -07:00
James Dunn
a8834c7766 First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. 2020-09-02 12:48:44 -07:00
Zitao Fang
85069387c9 Base Scratchpad 2020-07-08 14:45:12 -07:00
Paul Rigge
f56e367d59 Merge remote-tracking branch 'origin/dev' into HEAD 2020-05-23 22:49:51 +00:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
David Biancolin
ebe993cefe Assemble the firrt-test.jar and put it in its own directory 2020-05-14 19:25:21 +00:00
Ryan Lund
35cba5dfae Dsptools examples (#457)
* Add c test files for DSPTools example

* Update tests Makefile to build DSPTools c tests

* Add DSPTools example configs to ConfigMixins and RocketConfigs

* Add dsptools and rocket-dsptools as dependancies for example

* Add Scala implementations of DSPTools test blocks

* Clean up GenericFIR scala

* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial

* Update documentation, will need reworking once FIR is characterized as fixed point

* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain

* Fix capitalization in docs (#419)

* Add c test files for DSPTools example

* Update tests Makefile to build DSPTools c tests

* Add DSPTools example configs to ConfigMixins and RocketConfigs

* Add dsptools and rocket-dsptools as dependancies for example

* Add Scala implementations of DSPTools test blocks

* Clean up GenericFIR scala

* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial

* Update documentation, will need reworking once FIR is characterized as fixed point

* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain

* Update docs/Customization/Dsptools-Blocks.rst

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

* Docummentation update for clarity and to explain how this can be applied to a generalized block

* Some refactoring to get dsptools working with these examples

* Oops, old files crept in

Co-authored-by: Ryan Lund <ryan.lund@bwrcrdsl-4.eecs.berkeley.edu>
Co-authored-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
2020-04-20 10:33:03 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00
David Biancolin
7a17323bed [firechip] Isolate all firesim-multiclock stuff in a single file 2020-03-19 10:00:17 -07:00
Abraham Gonzalez
d0bec3fba7 Ariane Integration (#448)
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim
2020-03-09 18:06:41 -07:00
Jerry Zhao
854e71a205 Add tutorial config and tutorial patches 2020-03-05 19:44:37 -08:00
Howard Mao
24fe57d447 use blackboxed SimDRAM instead of SimAXIMem 2020-03-02 20:49:20 -08:00
Jerry Zhao
ebfa545344 Generator unification 2020-02-13 12:33:28 -08:00
Jerry Zhao
49dbe8daba Rename top-level example package to chipyard
* FireChip now directly uses the Chipyard Top
2020-02-13 12:33:04 -08:00
Jerry Zhao
05f17f5b99 [tracegen] Add tracegen support for the BOOM L1D (#362)
* [tracegen] Add tracegen support for the BOOM L1D

* [tracegen] Split up BOOM Tracegen mixin and shim.

* [ci] Fix tracegen hash for testing
2020-01-23 16:01:32 -08:00
Abraham Gonzalez
9e2726a251 Add UART and UARTAdapter to all configs (#348)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] bump testchipip | add small documentation in generators section
2020-01-16 11:33:46 -08:00
Howard Mao
cc564e0bfe add example NIC configuration 2019-12-16 09:02:01 -08:00
alonamid
56770a1a4c Gemmini Integration (#356)
* gemmini submodule

* fix build.sbt

* firechip gemmini config

* bump gemmini

* bump gemmini

* bump gemmini

* fix hwacha typo

* start gemmini docs

* bump gemmini

* gemmini docs

* Update Gemmini RST. Add quick-build instructions to Gemmini RST

* start gemmini CI

* bump gemmini

* gemmini CI fixes

* bump gemmini

* fix simulator name in gemmini CI

* cleanup gemmini CI

* bump esp-isa-sim to include gemmini

* update gemmini docs

* [ci skip] fix gemmini docs typos

* Update Gemmini.rst

Add instructions on building Gemmini programs, or writing your own programs.

* Changed order of VCS and Verilator in Gemmini docs

* Remove "make your own tests" from Gemmini README

* bump gemmini

* try to fix midasexamples CI
2019-12-14 01:36:42 -08:00
Colin Schmidt
86a473dbf6 Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
2019-12-12 13:39:09 -08:00
Albert Magyar
0d5bcf9c0d Add FireChip target with Verilog blackbox (#297)
Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>
2019-10-16 14:31:58 -07:00
Abraham Gonzalez
61d03fe37d update build.sbt for sha3 to build midastargetutils | have midas printf parameterized in sha3 2019-10-10 00:46:04 +00:00
David Biancolin
53f58f6baa Support serializable endpoints; Golden Gate stage 2019-10-04 14:54:26 -07:00
Albert Ou
d1e3cc558b firechip: Add FireSimRocketChipSha3L2Config 2019-10-04 01:09:53 +00:00
Albert Magyar
c2ce173195 Add Verilog MMIO GCD peripheral example 2019-09-26 01:47:31 -07:00