 abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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James Dunn
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95e8365105
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Small change to Arty reset binder name, per Jerry's PR comment.
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2020-11-18 16:53:37 -08:00 |
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abejgonzalez
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d94a8efd43
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Fix TLMemPort comment | Use Option instead of NoSimulator
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2020-11-15 15:44:38 -08:00 |
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abejgonzalez
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c8add488ad
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Reduce BOOM default freq. (play it safe)
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2020-11-15 14:31:14 -08:00 |
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abejgonzalez
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f8bd8eaa27
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Small fix to run_impl_bitstream
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2020-11-12 16:24:10 -08:00 |
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abejgonzalez
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61e1730c90
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Small fix to docs
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2020-11-12 16:23:05 -08:00 |
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abejgonzalez
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1b4826ad82
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Generalize debug-bitstream
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2020-11-12 16:20:22 -08:00 |
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abejgonzalez
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d4d989ce0f
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Rename make target to bitstream | Delete unused make stuff / tcl
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2020-11-12 15:41:05 -08:00 |
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abejgonzalez
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63b3d4290f
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Change NotSimulator to NoSimulator
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2020-11-12 15:39:57 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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999ae05bfe
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Address some docs, build.sbt, .gitmodules
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2020-11-12 15:31:34 -08:00 |
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abejgonzalez
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d5a0fd1a8e
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Address CircleCI
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2020-11-12 15:30:43 -08:00 |
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abejgonzalez
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7ca3be236c
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Bump bringup VCU118 | Ignore HTIF if no-debug module
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2020-11-12 11:47:16 -08:00 |
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dunn
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714fb56423
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Addressing PR comments in docs.
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2020-11-09 14:56:54 -08:00 |
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Abraham GonzalezandGitHub
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41454650e7
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Merge pull request #7 from ucb-bar/local-fpga-support-more-modular
Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:51:37 -08:00 |
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abejgonzalez
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082b230452
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Add missing file
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2020-11-08 17:51:21 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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abejgonzalez
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38a6bae872
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Add CI for Arty/VCU118 (just verilog)
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2020-11-07 17:27:19 -08:00 |
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abejgonzalez
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9c12ce08b7
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Create new prototyping section | Address some comments | Small clarifications
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2020-11-07 17:05:39 -08:00 |
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Abraham GonzalezandGitHub
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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Abraham GonzalezandGitHub
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a9b9054120
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Merge pull request #5 from ucb-bar/local-fpga-temp
Local fpga temp
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2020-11-06 21:02:17 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
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2020-11-06 21:00:18 -08:00 |
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Abraham Gonzalez
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9144e3c706
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Fix pin mappings for TSI DDR
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2020-11-06 20:51:11 -08:00 |
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James Dunn
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8fb76dda7b
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Fixed syntax.
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2020-11-06 20:00:29 -08:00 |
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James Dunn
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e20311da84
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Adding implementation details for the Arty.
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2020-11-06 19:58:52 -08:00 |
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James Dunn
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98fcea7b57
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Adding initial Arty documentation; will be expanded further.
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2020-11-06 17:25:05 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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6aae66c54f
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Add TSI Host Widget
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2020-11-06 15:50:28 -08:00 |
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abejgonzalez
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b7ef848605
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Add some docs on debugging
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2020-11-06 11:13:27 -08:00 |
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Abraham Gonzalez
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b0eed5075f
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[temp] start integrating tsi host widget
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2020-11-06 10:57:55 -08:00 |
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abejgonzalez
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c721d897f3
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Point to SiFive license | Add require on Arty
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2020-11-06 10:18:10 -08:00 |
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abejgonzalez
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84508bee6e
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More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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313fa4f129
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Merge branch 'local-fpga-support' into local-fpga-support-docs
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2020-11-05 21:24:03 -08:00 |
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abejgonzalez
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b0fc0457aa
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Use Chipyard configs as base (Arty)
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2020-11-05 20:46:03 -08:00 |
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abejgonzalez
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9a5b67bf8c
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Use Chipyard configs as a base (VCU118)
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2020-11-05 20:30:49 -08:00 |
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abejgonzalez
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255e88fe8f
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Initial outline of FPGA prototyping docs
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2020-11-05 17:06:34 -08:00 |
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abejgonzalez
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083f34ab23
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Revert Chipyard system | Create new VCU118 Chipyard system
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2020-11-05 15:44:54 -08:00 |
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abejgonzalez
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43e64ded93
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Readd ignore fpga-shells in main submodule setup
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2020-11-05 15:13:09 -08:00 |
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abejgonzalez
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a281869041
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Fix Arty merge and errors from CY bump
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2020-11-05 15:04:44 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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abejgonzalez
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356fa70c3c
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Update fpga-shells submodule | Fix Arty Makefile lines
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2020-11-05 11:16:17 -08:00 |
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abejgonzalez
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3994bcecdf
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Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
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2020-11-05 11:08:36 -08:00 |
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abejgonzalez
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c619df2c00
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Merge branch 'local-fpga-temp' into local-fpga-support
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2020-11-05 11:01:56 -08:00 |
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David BiancolinandGitHub
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c083d5d947
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Merge pull request #707 from ucb-bar/simple-pll-fixes
Update Reference Frequency Selection for Divider-Only Clock Generator
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2020-11-05 09:59:54 -05:00 |
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David Biancolin
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f504b7a0f5
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[clocking] Improve reference clock selection using a multiple-of-fastest strategy
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2020-11-03 09:14:55 -08:00 |
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David Biancolin
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aa4a44925e
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[clocking] Add ScalaTests for the divider-only PLL configurator
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2020-11-03 09:14:55 -08:00 |
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David Biancolin
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f387634a41
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[clocking] Bound SimplePllConfiguration by maximum reference freq
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2020-11-03 09:14:55 -08:00 |
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David BiancolinandGitHub
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946a191221
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[clocking] Provide a default div for ClockDividerN sv implementation (#706)
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2020-11-03 12:14:18 -05:00 |
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David BiancolinandGitHub
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57a0bc5dfc
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Fix zsh compatibility in init-submodules-no-rv-tools (#705)
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2020-11-03 12:14:02 -05:00 |
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Jerry ZhaoandGitHub
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37415157d6
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Merge pull request #699 from ucb-bar/lazy-iobinders
Support diplomatic IOBinders
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2020-11-02 20:14:54 -08:00 |
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