Commit Graph

160 Commits

Author SHA1 Message Date
abejgonzalez
0509c0c636 Merge remote-tracking branch 'origin/dev' into local-fpga-support 2020-12-30 09:34:14 -08:00
abejgonzalez
ec1efc150e Add small comment 2020-12-29 21:26:23 -08:00
abejgonzalez
6f9dcf5478 Add new SSH key to access build server 2020-12-29 20:51:29 -08:00
abejgonzalez
06dccdb588 Organize check commit CI printout | Don't copy .git folder in CI 2020-12-29 13:28:59 -08:00
abejgonzalez
cb488b8137 Init fpga-shells submod in CI 2020-12-27 22:49:24 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
abejgonzalez
5c7c1295a1 Bump Gemmini+Dsptools | Fix SBT_OPTs in CI 2020-12-11 11:37:25 -08:00
abejgonzalez
7f9cd0f012 Bump FireSim | CI Fix Attempt: Increase heap 2020-12-02 21:51:58 -08:00
abejgonzalez
3bc1bdb841 Bump BOOM | Split JAVA/SBT options in CI 2020-12-02 15:49:35 -08:00
abejgonzalez
d5a0fd1a8e Address CircleCI 2020-11-12 15:30:43 -08:00
David Biancolin
098a83ce98 [CI] Add a multiclock config 2020-11-09 09:26:30 -08:00
abejgonzalez
38a6bae872 Add CI for Arty/VCU118 (just verilog) 2020-11-07 17:27:19 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
Jerry Zhao
035e2e4315 Add test for make TOP=DigitalTop 2020-10-17 22:55:07 -07:00
Zitao Fang
93a06cc5e7 Fix CI master check 2020-10-01 10:11:04 -07:00
Zitao Fang
6641c1f983 Attempt to fix CI 2020-09-24 22:42:49 -07:00
Zitao Fang
ae5fb8470b Remove unnecessary CI tests 2020-09-19 10:27:20 -07:00
Zitao Fang
56d1d5b500 Fix CI errors 2020-09-18 22:42:19 -07:00
Zitao Fang
0c8771c35e Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-09-18 22:33:42 -07:00
Zitao Fang
a43400acb9 Update CI 2020-09-18 15:36:33 -07:00
Jerry Zhao
b9622c5132 Merge remote-tracking branch 'origin/dev' into serial-tl 2020-09-18 01:00:13 -07:00
Jerry Zhao
6874308981 Address review comments 2020-09-16 15:43:25 -07:00
Jerry Zhao
269af01a70 Bump testchipip 2020-09-16 13:51:33 -07:00
Jerry Zhao
aa8b7c15ec Reduce CI redundancy by grouping builds 2020-09-16 00:57:05 -07:00
Zitao Fang
1543acfacd Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate 2020-09-14 23:55:05 -07:00
Zitao Fang
5506f77679 Add CircleCI check and update Sodor config 2020-09-14 09:14:57 -07:00
Jerry Zhao
6c5bce5430 Support Tilelink over serial 2020-09-13 11:59:16 -07:00
Jerry Zhao
b613c14f1c Fix remaining HarnessBinders bugs 2020-09-04 20:03:12 -07:00
Jerry Zhao
20013d1348 Add DTM based bringup to regressions 2020-08-28 14:31:00 -07:00
Jerry Zhao
933df4e05c Whitelist firemarshal's dev branch for commit-on-master check 2020-08-27 23:27:24 -07:00
Jerry Zhao
ee1ce1141c Merge pull request #614 from ucb-bar/diplomatic-clocks
Diplomatic multiclock
2020-08-27 21:09:54 -07:00
Abraham Gonzalez
d402825e7f Change eval. strategy 2020-08-17 17:15:05 -07:00
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
863f723708 Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix
* Fixes bug with AXI4 MMIO ports not being generated properly due to
   IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
   appear in ChipTop
 * Change IOBinders to also require passing p: Parameters
   to child functions. Serialization of type targets via ClassTags fails
   for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
   as the type target in OverrideIOBinders.
2020-06-30 13:42:06 -07:00
Jerry Zhao
71f340a0af Use output_dir for run-binary logs and waveforms (#596)
* Dump run-binary files in output/$(long_name) instead of current directory
* Remove run-none rules, these were equivalent to run-binary BINARY=none
2020-06-12 10:08:55 -07:00
Jerry Zhao
623bafacd5 Warn if RISCV unset (#601) 2020-06-10 14:46:53 -07:00
abejgonzalez
5c3a7c136b [ci] remove midas-examples ci 2020-05-31 23:20:38 -07:00
abejgonzalez
4e09d91faa bump firemarshal/hammer-mentor-plugins | add submodules to check script 2020-05-28 16:27:58 -07:00
Abraham Gonzalez
a1717e4032 Merge pull request #568 from ucb-bar/dev-dsptools
Dsptools example cleanup
2020-05-28 15:25:09 -07:00
abejgonzalez
4972866b40 add coursier cache to firesim/midas tests 2020-05-28 13:50:19 -07:00
abejgonzalez
bbc03f6235 cleanup old folders in ci | add coursier cache export 2020-05-28 13:28:34 -07:00
Paul Rigge
e6984e412b Use Chain for dsptools example.
Rename examples, bump dsptools to master, and incorporate feedback.
2020-05-26 23:00:37 +00:00
Paul Rigge
7c074661d5 Add CI for dsptools examples 2020-05-25 20:27:58 +00:00
abejgonzalez
d2060947b6 bump toolchain version | fix git submodule update 2020-05-19 21:21:10 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
John Wright
7c7b336c3f Add SPI flash support (#546)
* Add SPI flash configs, IOBinders, CI tests, and docs

* Add writable SPI flash support

* bump

* Fix CI

* Fix CI

* Update docs/Generators/TestChipIP.rst

Co-authored-by: Chick Markley <chick@qrhino.com>

* Maybe actually fix CI

* Fix broken merge

* Fix the tutorial patch

* bump tcip to master

* fix GPIO naming bug

Co-authored-by: Chick Markley <chick@qrhino.com>
2020-05-14 19:19:50 -07:00
alonamid
3e57a5f539 Merge pull request #544 from ucb-bar/firrtl-1.3-RC-bump
Rocket Chip Bump with Chisel 3.3 and FIRRTL 1.3
2020-05-13 16:39:50 -07:00
abejgonzalez
460455e790 extend midas examples timeout in ci 2020-05-13 13:18:06 -07:00
Albert Magyar
2a6bd3bd5c Bump verilator to v4.034 (#547)
* Bump verilator to v4.034
* Add new flags to verilator makefile
* Conditionally set timescale flag based on Verilator version
2020-05-11 23:02:37 -07:00