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711 Commits

Author SHA1 Message Date
Abraham Gonzalez
79eccceadd Small comments to Clocks.scala 2021-02-27 22:55:25 +00:00
Jerry Zhao
1e2f778a67 Bump gemmini for config changes 2021-02-25 23:00:39 -08:00
abejgonzalez
6145b1df40 Use "tile" instead of "core" to assign freq's 2021-02-25 21:25:03 -08:00
David Biancolin
7f5d8c8dba Update frequency selection related comments 2021-02-24 13:05:14 -08:00
Jerry Zhao
2736e948ab Bump Gemmini for FP configs 2021-02-18 12:43:09 -08:00
Jerry Zhao
5966588d68 Merge pull request #790 from ucb-bar/simdram_timings 
Passing MBus clock frequency to SimDRAM
 2021-02-17 23:10:51 -08:00
Tynan McAuley
01948f6cb5 docs: Fix dual-BOOM-Rocket-Hwacha documentation 
The docs indicate that this should be a dual-BOOM and single-Rocket
config, with the Hwacha attached to the Rocket. However, the
'LargeBoomAndHwachaRocketConfig' config only has a single Rocket core.
Added the 'DualLargeBoomAndHwachaRocketConfig' config to accurately
reflect what's stated in the docs.

Additionally, this fixes hart numbering to place the Hwacha accelerator
on the Rocket core rather than on the BOOM core.
 2021-02-11 16:02:59 -08:00
Tynan McAuley
851df86aba docs: Fix dual-BOOM-single-Rocket documentation 
There were two problems here:
    1. The docs indicated that this should be a dual-BOOM and
       single-Rocket config, but the config actually had two Rocket
       cores.
    2. Since the doc include string was 'DualBoomAndRocket', it was
       accidentally matching against the 'DualBoomAndRocketOneHwacha'
       section, which comes first in the file.

So, I created a new 'DualLargeBoomAndSingleRocketConfig' config which
only has one Rocket core, and changed the doc include string to
'DualBoomAndSingleRocket'.
 2021-02-11 14:55:36 -08:00
Jerry Zhao
4c11e170b8 Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay 2021-02-09 00:47:10 -08:00
Jerry Zhao
235b1e5dfd Give TraceGenConfigs an explicit mbus clock 2021-02-08 09:03:15 -08:00
Jerry Zhao
c85ffd2a59 Add support for manually adjusting DRAM latency with a ShiftQueue 2021-02-08 03:14:48 -08:00
Jerry Zhao
0593e92cb3 Passing MBus clock frequency to SimDRAM 2021-02-08 02:11:18 -08:00
alonamid
6dcd4f9afc WithFireSimFAME5 to allow non Rocket/BOOM build 2021-02-01 17:33:07 -08:00
Jerry Zhao
99a1c5d542 Update comment on GenerateReset 
ChipTop reset was standardized to be async for 1.4.0
 2021-01-30 19:47:27 -08:00
Albert Magyar
f7a98f23bc Merge pull request #756 from ucb-bar/16-largeboom 
Add 16-core LargeBOOM config to firechip
 2021-01-13 15:36:51 -08:00
Albert Magyar
c481dc2ee8 Add 16-core LargeBOOM config to firechip 
* Fix Jerry's comment on accidentally mixing multiple BOOM configs
 2021-01-12 23:12:10 -08:00
Jerry Zhao
f624609331 Merge remote-tracking branch 'origin/dev' into sodor-testchipip-bump 2021-01-10 23:46:30 -08:00
Jerry Zhao
4156bd8513 Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading 2021-01-10 23:39:16 -08:00
Jerry Zhao
b1b230ba01 Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem 2021-01-10 23:38:11 -08:00
abejgonzalez
5505aef30f Bump sifive-blocks 2021-01-08 10:56:30 -08:00
abejgonzalez
4d3ff26a73 Bump testchipip 2021-01-04 15:36:00 -08:00
abejgonzalez
a6ca3d21ad Bump testchipip 2020-12-28 16:07:57 -08:00
abejgonzalez
b1cedf2d61 Make TinyRocketConfig work with multi-clock work 2020-12-28 09:55:10 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
Tim Snyder
0f47d80edb bump boom along same PR 2020-12-23 15:00:57 +00:00
Tim Snyder
e22350092b bump boom along same PR 2020-12-21 18:27:47 +00:00
Tim Snyder
29ab6301e0 bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 
my previous bump duplicated an earlier PR
 2020-12-21 18:15:49 +00:00
Tim Snyder
72d084da8f update parameter classes for RC additions 2020-12-18 23:24:19 +00:00
Tim Snyder
a7e6de835a rm *XTypeKey. upstreamed to RC 2020-12-18 23:22:03 +00:00
Tim Snyder
cb558b5952 bump boom along same PR 2020-12-18 23:20:31 +00:00
Tim Snyder
a2ce14f8d3 Bump sodor for ucb-bar/riscv-sodor#60 2020-12-18 21:03:12 +00:00
Tim Snyder
2ce5f6a407 Bump cva6 for ucb-bar/cva6-wrapper#11 2020-12-18 20:54:31 +00:00
Tim Snyder
022dbf976f Bump boom along in the same PR 2020-12-18 20:52:30 +00:00
Tim Snyder
f7a372153a Bump hwacha for ucb-bar/hwacha#24 2020-12-18 20:52:00 +00:00
Tim Snyder
5ff5b4e8b7 Bump sifive-cache for sifive/block-inclusivecache-sifive#18 2020-12-18 20:05:29 +00:00
Tim Snyder
c6dfa1d8c5 Bump testchipip for ucb-bar/testchipip#111 2020-12-18 18:03:51 +00:00
Tim Snyder
95420baccf Bump boom for riscv-boom/riscv-boom#508 
non-master pre-merge bump
 2020-12-18 18:00:30 +00:00
Tim Snyder
f693972e12 Start RC bump 
Bump to pre-merge chipsalliance/rocket-chip#2764 to get it
going while picking up the chisel/firrtl bugfixes in 3/1.4.1+
 2020-12-18 18:00:21 +00:00
David Biancolin
1bd51447fe [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala 
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2020-12-13 10:45:51 -05:00
David Biancolin
8f1e20936f Update FireSim CI. Push threading into test context 2020-12-12 13:41:32 -08:00
abejgonzalez
98a3e443ce Merge remote-tracking branch 'origin/dev' into local-chisel34 2020-12-11 15:08:02 -08:00
abejgonzalez
fe4aa6cade Bump BOOM/Gemmini 2020-12-11 14:20:09 -08:00
abejgonzalez
5c7c1295a1 Bump Gemmini+Dsptools | Fix SBT_OPTs in CI 2020-12-11 11:37:25 -08:00
abejgonzalez
d4d483c081 Bump BOOM | Use ucb-bar fork chisel-testers 2020-12-11 10:19:02 -08:00
David Biancolin
ee436c9b3f [firechip] Fix a uart multiclock bug 2020-12-10 07:18:12 +00:00
David Biancolin
1787fda8c3 Bump icenet 2020-12-10 06:34:39 +00:00
David Biancolin
76ba68b02f Bump hwacha 2020-12-10 06:34:30 +00:00
abejgonzalez
f1df2ec69e Bump FireSim/Hwacha | Cleanup linting 2020-12-03 12:51:24 -08:00
abejgonzalez
3bc1bdb841 Bump BOOM | Split JAVA/SBT options in CI 2020-12-02 15:49:35 -08:00
abejgonzalez
145885390f Bump Hwacha 2020-12-02 15:08:06 -08:00