Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
* Fixes bug with AXI4 MMIO ports not being generated properly due to
IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
appear in ChipTop
* Change IOBinders to also require passing p: Parameters
to child functions. Serialization of type targets via ClassTags fails
for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
as the type target in OverrideIOBinders.
* [uart] add uart adapter | add uart + adapter to all configs
* [uart] change pty define name | add uart to all configs that need it
* [uart] default to 115200 baudrate
* [dromajo] first working commit
* [dromajo] bump boom for commit-width > 1 fix
* [dromajo] adjust dromajo commits
* [dromajo] bump boom
* commit dromajo changes
* extra
* [dromajo] add block device to configs
* rebump older modules
* bump firesim
* [chipyard] enable dromajo in midas level simulation
* [testchipip] forgot to bump
* get rid of breaking things
* bump firesim
* bump boom
* Bump BOOM to ifu3 WIP
* bump firesim
* fix how memory is passed to dromajo
* bump boom and firesim
* fix merge issues
* add dromajo cosim bridge in chipyard
* move traceio back into testchipip (#488)
* refer to testchipip traceio in firechip (#490)
* Move TraceIO fragment to chipyard (#492)
* fix chipyard dromajo bridge (#493)
* Sboom dromajo bump (#501)
* [FireChip] Use clock in BridgeBinders
* [firesim] Update TraceGen BridgeBinder
* [Firechip] Add support for Tile <-> Uncore rational division
* [firesim] Update the multiclock test
* [firechip] Commit some Eagle X-related mock configs
* [firechip] Instantiate multiple TracerV bridges
* [Firechip] Include reset in tracerv tokens
* [TracerV] Drop the first token in comparison tests
* [Firechip] Make reverse instruction order in trace printf
* WARNING: Point at a fork of boom @ davidbiancolin
* [firesim] Update ClockBridge API
* Add Gemmini to README [ci skip] (#487)
* [firechip] Isolate all firesim-multiclock stuff in a single file
* add documentation on ring network and system bus
* Bump firesim for CI
* Bump FireSim
* Bump testchipip to dev
[ci skip]
* Bump FireSim
* [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags
* [make] move dramsim and max-cycles into SIM_FLAGS
* [misc] move ariane configs to configs/ folder
* [dromajo] add dromajo
* [dromajo] bump for new traceio changes
* bump firesim
* bump firesim
* point to chipyard traceio
* bump boom
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
* Support Dromajo + TracerV configurations
* [docs] add documentation for Dromajo in FireSim + Chipyard
* add a bit more docs
* [docs] bump docs
* [firesim] dump artefacts in firesim
* [firesim] update firesim
* [testchipip] remove extraneous items in testchipip
* [dromajo] prevent dromajo from breaking when params unset
* update firesim, dromajo, and testchipip
* [firesim] bump firesim
* [firesim] bump firesim
* [misc] bump firesim and testchipip for reviewer comments
* remove WithNoGPIO fragment
* bump firesim
* bump dromajo boom config
* bump firesim
* generate artefacts in firesim testsuite
Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
