Jerry Zhao
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4d928c3c14
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Rename timeout_cycles to TIMEOUT_CYCLES to match convention
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2023-12-18 13:47:48 -08:00 |
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Nayiri
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700057d9eb
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changed chiptop dut name, set FSDB=1 when needed
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2023-11-13 13:33:24 -08:00 |
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Nayiri K
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dcaca02e14
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small fixes for sim yaml generation
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2023-06-30 15:04:04 -07:00 |
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Jerry Zhao
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4da1dea50f
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Support multi-binary-run in RTL sim
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2023-05-24 16:48:18 -07:00 |
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joey0320
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a5bf60c0f1
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oops
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2023-04-29 21:32:00 -07:00 |
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joey0320
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9ce0467bd3
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fixes
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2023-04-20 14:26:38 -07:00 |
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Harrison Liew
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0883993000
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model and top reference common modules, need to filter them out from sim to avoid module collisions
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2023-03-08 16:11:01 -08:00 |
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Harrison Liew
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c1e8b20234
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add SIM_FILE_REQS
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2023-02-27 15:24:00 -08:00 |
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Harrison Liew
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a681bedae0
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fix top/model separation for rtl vs. post-syn/par sim
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2023-02-24 20:37:36 -08:00 |
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Sagar Karandikar
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97f576da2a
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Same as Makefile
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2023-02-15 18:26:30 -08:00 |
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Harrison Liew
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83764d3329
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[skip ci] add power-rtl and power-syn targets
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2023-02-09 13:01:08 -08:00 |
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Harrison Liew
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a7214e671c
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TinyRocketConfig thru par. sim runs, but gl-sim times out.
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2021-06-06 20:19:42 -07:00 |
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Harrison Liew
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81b57f96bd
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hier helper make targets
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2021-05-17 14:56:09 -07:00 |
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Harrison Liew
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840eb9fdeb
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par -> syn typo
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2021-04-15 10:00:14 -07:00 |
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Harrison Liew
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87a1064366
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add timing annotated targets for post-syn sim + docs update
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2021-04-15 09:36:07 -07:00 |
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Colin Schmidt
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e403730315
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More fixes for post-syn/par hammer simulations
Symlink dramsim2 into hammer-sims rundirs
update some hammer generated makefile targets that were missed before
bump barstools to get an iocell fix
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2020-05-29 15:13:37 -07:00 |
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Colin Schmidt
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422e7fd4e6
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Bump hammer for last pre-merge fixes, update make target names
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2020-05-26 13:36:13 -07:00 |
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Colin Schmidt
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b17de6a4dd
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Hide my sins
Also begin power integration
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2020-03-20 16:30:32 -07:00 |
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