Abraham Gonzalez
|
db73cab164
|
Add BootROM | Fix ResetWrangler for DDR | Add scripts
|
2020-10-20 21:20:11 -07:00 |
|
Abraham Gonzalez
|
dd358f45ab
|
UART Working... Bumped to newer fpga-shells
|
2020-10-19 11:29:25 -07:00 |
|
abejgonzalez
|
9ba4918cb8
|
Inject MMCDevice into TLSPI Node
|
2020-10-15 11:46:42 -07:00 |
|
abejgonzalez
|
7f387a254b
|
Working up until the MMC attachment
|
2020-10-14 23:09:49 -07:00 |
|
abejgonzalez
|
dcac9b79df
|
Basic working with UART
|
2020-10-14 16:15:10 -07:00 |
|
abejgonzalez
|
949d60597f
|
Revert "Support evaluation of HarnessBinders in LazyModule context"
This reverts commit 9c298eedfe.
|
2020-10-14 14:50:38 -07:00 |
|
abejgonzalez
|
dda7622c29
|
temp commit
|
2020-10-14 14:49:22 -07:00 |
|
abejgonzalez
|
341a6cc48d
|
Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp
|
2020-10-13 16:23:41 -07:00 |
|
abejgonzalez
|
5bbd865447
|
Add MMC Device section to the DTS
|
2020-10-13 16:18:00 -07:00 |
|
Jerry Zhao
|
9c298eedfe
|
Support evaluation of HarnessBinders in LazyModule context
|
2020-10-13 15:10:41 -07:00 |
|
abejgonzalez
|
8257775e96
|
Connect DDR from harness
|
2020-10-12 21:50:50 -07:00 |
|
Jerry Zhao
|
8f86b6d19a
|
Merge pull request #683 from ucb-bar/unify-fesvr
Unify htif implementation with firesim
|
2020-10-12 11:17:23 -07:00 |
|
Jerry Zhao
|
0c46ed1676
|
Rename testchip_fesvr to testchip_tsi
|
2020-10-09 09:34:20 -07:00 |
|
Jerry Zhao
|
25129c27ca
|
Add testchip_fesvr to uncondtionally used resources
|
2020-10-09 09:27:58 -07:00 |
|
Jerry Zhao
|
d71c3b6357
|
Unify htif implementation with firesim
|
2020-10-09 09:27:58 -07:00 |
|
Jerry Zhao
|
b583276d1e
|
Merge pull request #682 from ucb-bar/clocking-features
Add tile-reset control registers | multiclock fixes
|
2020-10-08 14:39:53 -07:00 |
|
Nathan Pemberton
|
bf8dbaa297
|
Merge pull request #689 from ucb-bar/bumpMarshal1.10
Bump firemarshal to v1.10.0
|
2020-10-08 11:07:23 -07:00 |
|
Nathan Pemberton
|
399b909dec
|
Bump firemarshal to v1.10.0
|
2020-10-07 20:50:26 -04:00 |
|
Jerry Zhao
|
3d0022667a
|
Bump testchipip
|
2020-10-01 22:43:43 -07:00 |
|
Jerry Zhao
|
b057cfbd8c
|
Merge remote-tracking branch 'origin/dev' into clocking-features
|
2020-10-01 20:12:20 -07:00 |
|
Jerry Zhao
|
2db3c90f83
|
Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
|
2020-10-01 17:31:45 -07:00 |
|
Albert Magyar
|
fb519e7b83
|
Merge pull request #679 from ucb-bar/add-multithreading-annos
Add model multi-threading annotations (ignored by default) to FireChip
|
2020-10-01 14:23:54 -07:00 |
|
Jerry Zhao
|
79042e4ce8
|
Bump to support firesim simulation of no-AXI4DRAM designs
|
2020-10-01 10:21:43 -07:00 |
|
Jerry Zhao
|
164617e2d6
|
Fix no-mbus example design
|
2020-10-01 10:20:10 -07:00 |
|
Jerry Zhao
|
489ae695fc
|
Add tile-resetter to all designs
|
2020-10-01 10:19:43 -07:00 |
|
Zitao Fang
|
93a06cc5e7
|
Fix CI master check
|
2020-10-01 10:11:04 -07:00 |
|
Zitao Fang
|
6c33672c66
|
Bump Sodor submodule after merge
|
2020-10-01 10:08:39 -07:00 |
|
Albert Magyar
|
2f5790d611
|
Add model multi-threading annotations (ignored by default) to FireChip
|
2020-09-30 23:32:49 -07:00 |
|
David Biancolin
|
45d40eb2af
|
Merge pull request #676 from ucb-bar/diplomatic-clocks-pll-redux
Simple Divider-Only PLL for Multiclock RTL Simulation
|
2020-09-30 22:30:35 -07:00 |
|
David Biancolin
|
7d7f7ae4a8
|
Bump FireSim
|
2020-09-30 14:43:29 -07:00 |
|
Zitao Fang
|
ef03a5efe0
|
Bump testchipip
|
2020-09-30 14:36:45 -07:00 |
|
David Biancolin
|
ebfe3103a4
|
[clocks] IdealizedPll -> DividerOnlyClockGenerator
|
2020-09-29 17:33:49 -07:00 |
|
David Biancolin
|
5b414f5829
|
[clocks] Emit frequency summary for divider-only PLL model
|
2020-09-29 16:59:37 -07:00 |
|
David Biancolin
|
a6ce850391
|
[clocks] ClockDividerN: make first output edge occur on first input edge
|
2020-09-29 16:19:05 -07:00 |
|
Zitao Fang
|
f7407709d2
|
Attempt to fix CI (2)
|
2020-09-25 21:31:12 -07:00 |
|
Zitao Fang
|
942766ad86
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
|
2020-09-25 11:41:40 -07:00 |
|
David Biancolin
|
b76972d34b
|
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
|
2020-09-25 11:02:51 -07:00 |
|
David Biancolin
|
67145c6ccd
|
[clocking] Fix FireSim clock look up
|
2020-09-25 10:05:28 -07:00 |
|
David Biancolin
|
1b3514f95f
|
[clocks] Specify a default frequency for TraceGen
|
2020-09-25 10:03:46 -07:00 |
|
David Biancolin
|
7b8a954d04
|
[firechip] Rework FireSim clocking to be more similar to default CY targets
|
2020-09-24 23:32:07 -07:00 |
|
David Biancolin
|
cc949aadab
|
[clocking] Address some of Colin's PR comments
|
2020-09-24 23:28:47 -07:00 |
|
David Biancolin
|
f6989a1968
|
[clocks] Use the periphery frequency as the default
|
2020-09-24 23:24:08 -07:00 |
|
David Biancolin
|
96bf702c3b
|
[clocks] Factor out the PLL calculations into their own class
|
2020-09-24 23:23:11 -07:00 |
|
Zitao Fang
|
6641c1f983
|
Attempt to fix CI
|
2020-09-24 22:42:49 -07:00 |
|
David Biancolin
|
84195d28bb
|
[clocks] Don't override existing take frequency if present.
|
2020-09-23 15:29:52 -07:00 |
|
Jerry Zhao
|
023d8096a9
|
Merge pull request #677 from ucb-bar/smartelf2hex-fix
Fix smartelf2hex.sh creating files 64x the minimum size
|
2020-09-22 17:04:45 -07:00 |
|
Jerry Zhao
|
d5660c01f3
|
Bump esp-isa-sim for loadmem-fix add TLS segments to smartelf2hex
|
2020-09-22 12:58:34 -07:00 |
|
Jerry Zhao
|
6c297e3179
|
Fix smartelf2hex.sh creating files 64x the minimum size
|
2020-09-22 11:08:52 -07:00 |
|
Zitao Fang
|
ae5fb8470b
|
Remove unnecessary CI tests
|
2020-09-19 10:27:20 -07:00 |
|
Zitao Fang
|
a02700a1d4
|
Add documentation for sodor
|
2020-09-18 23:14:47 -07:00 |
|