Nayiri
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3a6677bc30
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Fix clock name and macro paths for Sky130 VLSI flow (#1882)
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2024-05-19 17:54:47 -07:00 |
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Nayiri
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42622919cd
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fixing macro paths for yosys with circt generated verilog [skip ci]
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2023-12-14 18:02:32 -08:00 |
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abejgonzalez
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088e9ea45a
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Remove references to ENABLE_YOSYS
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2023-12-13 10:07:14 -08:00 |
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abejgonzalez
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c7f1fe220d
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Enable precommit | Format files
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2023-08-28 14:56:55 -07:00 |
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Nayiri K
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222059941e
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renamed clock_clock to clock_uncore_clock
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2023-06-30 15:04:38 -07:00 |
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Nayiri Krzysztofowicz
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dd7e221a45
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changing tutorial VLSI_TOP to RocketTile to save time
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2023-03-12 19:04:14 -07:00 |
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