John Wright
d97afcdfbc
Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a
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bug using verilator, make the whitespace consistend in
Makefrag-verilator, explicitly name the verilog sources to match vsim,
and update verisim/Makefile to use the new source variable names
2019-02-13 21:13:08 -08:00
Albert Ou
cd82131748
verisim: Add verilator-harness.cc from testchipip/csrc
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This fixes #35 and matches firechip.
238afa543f49b7982c82
2018-10-05 09:24:35 -07:00
Howard Mao
4c8c6e29f0
update rocket-chip again
2018-04-18 17:13:07 -07:00
olix86
b599514934
Update Makefrag-verilator
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Changed verilator version from 3.904 to 3.920, which fixes a bug that prevented the default example to compile correctly
2018-04-17 17:11:30 -07:00
Howard Mao
7e70e3525f
move bootrom to testchipip
2018-04-17 15:13:47 -07:00
Howard Mao
d88c2fa84f
add regression tests to makefile
2018-02-23 13:48:45 -08:00
Howard Mao
91df4098f3
remove SimpleNIC
2017-08-31 11:06:41 -07:00
Howard Mao
ada96f3724
update verilator so that plusarg_reader works
2017-07-20 20:19:02 +00:00
Howard Mao
fae57b6daa
make sure verilator builds correctly
2017-07-20 19:44:23 +00:00
Howard Mao
cb6290539c
add network simulation C++ code
2017-07-01 19:58:31 -07:00
Howard Mao
119e563ea6
fix verilator build
2017-06-22 17:41:48 -07:00
Howard Mao
3e2b6a1d55
make clean should clean everything
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Also add "make clean" for verisim"
2017-06-07 17:14:46 -07:00
Howard Mao
adb8c80ab3
change up gitignore rules
2017-02-07 17:37:26 -08:00
Howard Mao
d22f0cab68
split verilator compilation into phases
2016-10-27 16:57:00 -07:00
Howard Mao
6c115b4234
add verilator simulation
2016-10-25 11:38:00 -07:00
