Nayiri Krzysztofowicz dd7e221a45 changing tutorial VLSI_TOP to RocketTile to save time

2023-03-12 19:04:14 -07:00

..

example-designs

changing tutorial VLSI_TOP to RocketTile to save time

2023-03-12 19:04:14 -07:00

hammer-cadence-plugins @ 902657b8bd

bumping hammer-cadence-plugins

2023-03-10 23:20:40 -08:00

hammer-mentor-plugins @ eca060af45

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

hammer-synopsys-plugins @ e53fa5c51f

support main or master as default branch in hammer plugins

2023-02-13 19:05:17 -08:00

.gitignore

OpenROAD synthesis complete with fake rams on nangate45

2020-06-18 13:55:33 -07:00

env.yml

[skip ci] address comments, remove bwrc env vars, bump hammer

2019-09-26 15:40:22 -07:00

example-asap7.yml

updating macro paths for asap7 tutorial to match new SRAM paths after rocket/chisel bump

2023-03-10 15:09:15 -08:00

example-design.yml

Run pre-commit on all files

2022-12-21 15:59:46 -08:00

example-openroad.yml

top blackbox isolation hack, bump submodules

2023-02-06 12:29:29 -08:00

example-sky130.yml

floorplan for openroad flow is different from commercial flow bc of srams

2023-03-10 23:18:20 -08:00

example-tech.yml

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

example-tools.yml

[skip ci] add power-rtl and power-syn targets

2023-02-09 13:01:08 -08:00

example-vlsi

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

example-vlsi-sky130

initial migration to new Hammer

2023-02-06 12:29:29 -08:00

Makefile

update ENABLE_VLSI_FLOW to ENABLE_YOSYS_FLOW

2023-03-08 09:25:16 -08:00

power.mk

fix & clarify hierarchical flows

2023-02-24 14:56:28 -08:00

sim.mk

model and top reference common modules, need to filter them out from sim to avoid module collisions

2023-03-08 16:11:01 -08:00

tutorial.mk

changing tutorial VLSI_TOP to RocketTile to save time

2023-03-12 19:04:14 -07:00

view_gds.py

view_gds.py update

2021-10-27 13:40:11 -07:00