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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 08:45:46 -04:00
parent 164eb5454c
commit 3139d37610
62 changed files with 261 additions and 256 deletions
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48
hw/rtl/VX_back_end.v
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@@ -9,49 +9,49 @@ module VX_back_end
input wire reset, input wire reset,
input wire schedule_delay, input wire schedule_delay,
VX_gpu_dcache_rsp_inter vx_dcache_rsp, VX_gpu_dcache_rsp_if vx_dcache_rsp,
VX_gpu_dcache_req_inter vx_dcache_req, VX_gpu_dcache_req_if vx_dcache_req,
output wire out_mem_delay, output wire out_mem_delay,
output wire out_exec_delay, output wire out_exec_delay,
output wire gpr_stage_delay, output wire gpr_stage_delay,
VX_jal_response_inter vx_jal_rsp, VX_jal_response_if vx_jal_rsp,
VX_branch_response_inter vx_branch_rsp, VX_branch_response_if vx_branch_rsp,
VX_frE_to_bckE_req_inter vx_bckE_req, VX_frE_to_bckE_req_if vx_bckE_req,
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
VX_warp_ctl_inter vx_warp_ctl VX_warp_ctl_if vx_warp_ctl
); );
VX_wb_inter vx_writeback_temp(); VX_wb_if vx_writeback_temp();
assign vx_writeback_inter.wb = vx_writeback_temp.wb; assign vx_writeback_if.wb = vx_writeback_temp.wb;
assign vx_writeback_inter.rd = vx_writeback_temp.rd; assign vx_writeback_if.rd = vx_writeback_temp.rd;
assign vx_writeback_inter.write_data = vx_writeback_temp.write_data; assign vx_writeback_if.write_data = vx_writeback_temp.write_data;
assign vx_writeback_inter.wb_valid = vx_writeback_temp.wb_valid; assign vx_writeback_if.wb_valid = vx_writeback_temp.wb_valid;
assign vx_writeback_inter.wb_warp_num = vx_writeback_temp.wb_warp_num; assign vx_writeback_if.wb_warp_num = vx_writeback_temp.wb_warp_num;
assign vx_writeback_inter.wb_pc = vx_writeback_temp.wb_pc; assign vx_writeback_if.wb_pc = vx_writeback_temp.wb_pc;
// assign VX_writeback_inter(vx_writeback_temp); // assign VX_writeback_if(vx_writeback_temp);
wire no_slot_mem; wire no_slot_mem;
wire no_slot_exec; wire no_slot_exec;
// LSU input + output // LSU input + output
VX_lsu_req_inter vx_lsu_req(); VX_lsu_req_if vx_lsu_req();
VX_inst_mem_wb_inter vx_mem_wb(); VX_inst_mem_wb_if vx_mem_wb();
// Exec unit input + output // Exec unit input + output
VX_exec_unit_req_inter vx_exec_unit_req(); VX_exec_unit_req_if vx_exec_unit_req();
VX_inst_exec_wb_inter vx_inst_exec_wb(); VX_inst_exec_wb_if vx_inst_exec_wb();
// GPU unit input // GPU unit input
VX_gpu_inst_req_inter vx_gpu_inst_req(); VX_gpu_inst_req_if vx_gpu_inst_req();
// CSR unit inputs // CSR unit inputs
VX_csr_req_inter vx_csr_req(); VX_csr_req_if vx_csr_req();
VX_csr_wb_inter vx_csr_wb(); VX_csr_wb_if vx_csr_wb();
wire no_slot_csr; wire no_slot_csr;
wire stall_gpr_csr; wire stall_gpr_csr;
@@ -59,7 +59,7 @@ VX_gpr_stage vx_gpr_stage(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.schedule_delay (schedule_delay), .schedule_delay (schedule_delay),
.vx_writeback_inter(vx_writeback_temp), .vx_writeback_if(vx_writeback_temp),
.vx_bckE_req (vx_bckE_req), .vx_bckE_req (vx_bckE_req),
// New // New
.vx_exec_unit_req(vx_exec_unit_req), .vx_exec_unit_req(vx_exec_unit_req),
@@ -124,7 +124,7 @@ VX_writeback vx_wb (
.vx_inst_exec_wb (vx_inst_exec_wb), .vx_inst_exec_wb (vx_inst_exec_wb),
.vx_csr_wb (vx_csr_wb), .vx_csr_wb (vx_csr_wb),
.vx_writeback_inter(vx_writeback_temp), .vx_writeback_if(vx_writeback_temp),
.no_slot_mem (no_slot_mem), .no_slot_mem (no_slot_mem),
.no_slot_exec (no_slot_exec), .no_slot_exec (no_slot_exec),
.no_slot_csr (no_slot_csr) .no_slot_csr (no_slot_csr)

2
hw/rtl/VX_csr_handler.v
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@@ -1,7 +1,7 @@
module VX_csr_handler ( module VX_csr_handler (
input wire clk, input wire clk,
input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done
VX_csr_write_request_inter vx_csr_w_req, VX_csr_write_request_if vx_csr_w_req,
input wire in_wb_valid, input wire in_wb_valid,
output wire[31:0] out_decode_csr_data // done output wire[31:0] out_decode_csr_data // done
); );

6
hw/rtl/VX_csr_pipe.v
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@@ -6,9 +6,9 @@ module VX_csr_pipe #(
input wire clk, // Clock input wire clk, // Clock
input wire reset, input wire reset,
input wire no_slot_csr, input wire no_slot_csr,
VX_csr_req_inter vx_csr_req, VX_csr_req_if vx_csr_req,
VX_wb_inter vx_writeback, VX_wb_if vx_writeback,
VX_csr_wb_inter vx_csr_wb, VX_csr_wb_if vx_csr_wb,
output wire stall_gpr_csr output wire stall_gpr_csr
); );

4
hw/rtl/VX_csr_wrapper.v
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@@ -2,8 +2,8 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_csr_wrapper ( module VX_csr_wrapper (
VX_csr_req_inter vx_csr_req, VX_csr_req_if vx_csr_req,
VX_csr_wb_inter vx_csr_wb VX_csr_wb_if vx_csr_wb
); );

8
hw/rtl/VX_decode.v
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@@ -3,12 +3,12 @@
module VX_decode( module VX_decode(
// Fetch Inputs // Fetch Inputs
VX_inst_meta_inter fd_inst_meta_de, VX_inst_meta_if fd_inst_meta_de,
// Outputs // Outputs
VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, VX_frE_to_bckE_req_if vx_frE_to_bckE_req,
VX_wstall_inter vx_wstall, VX_wstall_if vx_wstall,
VX_join_inter vx_join, VX_join_if vx_join,
output wire terminate_sim output wire terminate_sim

9
hw/rtl/VX_define.vh
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@@ -12,8 +12,13 @@
`define DEBUG_BEGIN /* verilator lint_off UNUSED */ `define DEBUG_BEGIN /* verilator lint_off UNUSED */
`define DEBUG_END /* verilator lint_on UNUSED */ `define DEBUG_END /* verilator lint_on UNUSED */
`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ `define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ /* verilator lint_off PINCONNECTEMPTY */ \
/* verilator lint_off DECLFILENAME */
`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
/* verilator lint_on PINCONNECTEMPTY */ \
/* verilator lint_on DECLFILENAME */
`define STRINGIFY(x) `"x`" `define STRINGIFY(x) `"x`"

60
hw/rtl/VX_dmem_controller.v
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@@ -5,29 +5,29 @@ module VX_dmem_controller (
input wire reset, input wire reset,
// Dram <-> Dcache // Dram <-> Dcache
VX_gpu_dcache_dram_req_inter vx_gpu_dcache_dram_req, VX_gpu_dcache_dram_req_if vx_gpu_dcache_dram_req,
VX_gpu_dcache_dram_rsp_inter vx_gpu_dcache_dram_res, VX_gpu_dcache_dram_rsp_if vx_gpu_dcache_dram_res,
VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req, VX_gpu_snp_req_rsp_if vx_gpu_dcache_snp_req,
// Dram <-> Icache // Dram <-> Icache
VX_gpu_dcache_dram_req_inter vx_gpu_icache_dram_req, VX_gpu_dcache_dram_req_if vx_gpu_icache_dram_req,
VX_gpu_dcache_dram_rsp_inter vx_gpu_icache_dram_res, VX_gpu_dcache_dram_rsp_if vx_gpu_icache_dram_res,
VX_gpu_snp_req_rsp vx_gpu_icache_snp_req, VX_gpu_snp_req_rsp_if vx_gpu_icache_snp_req,
// Core <-> Dcache // Core <-> Dcache
VX_gpu_dcache_rsp_inter vx_dcache_rsp, VX_gpu_dcache_rsp_if vx_dcache_rsp,
VX_gpu_dcache_req_inter vx_dcache_req, VX_gpu_dcache_req_if vx_dcache_req,
// Core <-> Icache // Core <-> Icache
VX_gpu_dcache_rsp_inter vx_icache_rsp, VX_gpu_dcache_rsp_if vx_icache_rsp,
VX_gpu_dcache_req_inter vx_icache_req VX_gpu_dcache_req_if vx_icache_req
); );
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_smem(); VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_smem();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_smem(); VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_smem();
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_dcache(); VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp_dcache();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_dcache(); VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_dcache();
wire to_shm = vx_dcache_req.core_req_addr[0][31:24] == 8'hFF; wire to_shm = vx_dcache_req.core_req_addr[0][31:24] == 8'hFF;
wire dcache_wants_wb = (|vx_dcache_rsp_dcache.core_wb_valid); wire dcache_wants_wb = (|vx_dcache_rsp_dcache.core_wb_valid);
@@ -66,8 +66,8 @@ module VX_dmem_controller (
assign vx_dcache_rsp.delay_req = to_shm ? vx_dcache_rsp_smem.delay_req : vx_dcache_rsp_dcache.delay_req; assign vx_dcache_rsp.delay_req = to_shm ? vx_dcache_rsp_smem.delay_req : vx_dcache_rsp_dcache.delay_req;
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_req(); VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_req();
VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_res(); VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_smem_dram_res();
VX_cache #( VX_cache #(
.CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES), .CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES),
@@ -118,9 +118,9 @@ module VX_dmem_controller (
.core_wb_warp_num (vx_dcache_rsp_smem.core_wb_warp_num), .core_wb_warp_num (vx_dcache_rsp_smem.core_wb_warp_num),
.core_wb_readdata (vx_dcache_rsp_smem.core_wb_readdata), .core_wb_readdata (vx_dcache_rsp_smem.core_wb_readdata),
.core_wb_pc (vx_dcache_rsp_smem.core_wb_pc), .core_wb_pc (vx_dcache_rsp_smem.core_wb_pc),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.core_wb_address (), .core_wb_address (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
// DRAM response // DRAM response
.dram_rsp_valid (vx_gpu_smem_dram_res.dram_rsp_valid), .dram_rsp_valid (vx_gpu_smem_dram_res.dram_rsp_valid),
@@ -140,15 +140,15 @@ module VX_dmem_controller (
// Snoop Request // Snoop Request
.snp_req_valid (0), .snp_req_valid (0),
.snp_req_addr (0), .snp_req_addr (0),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.snp_req_full (), .snp_req_full (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
// Snoop Forward // Snoop Forward
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.snp_fwd_valid (), .snp_fwd_valid (),
.snp_fwd_addr (), .snp_fwd_addr (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
.snp_fwd_full (0) .snp_fwd_full (0)
); );
@@ -201,9 +201,9 @@ module VX_dmem_controller (
.core_wb_warp_num (vx_dcache_rsp_dcache.core_wb_warp_num), .core_wb_warp_num (vx_dcache_rsp_dcache.core_wb_warp_num),
.core_wb_readdata (vx_dcache_rsp_dcache.core_wb_readdata), .core_wb_readdata (vx_dcache_rsp_dcache.core_wb_readdata),
.core_wb_pc (vx_dcache_rsp_dcache.core_wb_pc), .core_wb_pc (vx_dcache_rsp_dcache.core_wb_pc),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.core_wb_address (), .core_wb_address (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
// DRAM response // DRAM response
.dram_rsp_valid (vx_gpu_dcache_dram_res.dram_rsp_valid), .dram_rsp_valid (vx_gpu_dcache_dram_res.dram_rsp_valid),
@@ -226,10 +226,10 @@ module VX_dmem_controller (
.snp_req_full (vx_gpu_dcache_snp_req.snp_req_full), .snp_req_full (vx_gpu_dcache_snp_req.snp_req_full),
// Snoop Forward // Snoop Forward
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.snp_fwd_valid (), .snp_fwd_valid (),
.snp_fwd_addr (), .snp_fwd_addr (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
.snp_fwd_full (0) .snp_fwd_full (0)
); );
@@ -282,9 +282,9 @@ module VX_dmem_controller (
.core_wb_warp_num (vx_icache_rsp.core_wb_warp_num), .core_wb_warp_num (vx_icache_rsp.core_wb_warp_num),
.core_wb_readdata (vx_icache_rsp.core_wb_readdata), .core_wb_readdata (vx_icache_rsp.core_wb_readdata),
.core_wb_pc (vx_icache_rsp.core_wb_pc), .core_wb_pc (vx_icache_rsp.core_wb_pc),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.core_wb_address (), .core_wb_address (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
// DRAM response // DRAM response
.dram_rsp_valid (vx_gpu_icache_dram_res.dram_rsp_valid), .dram_rsp_valid (vx_gpu_icache_dram_res.dram_rsp_valid),
@@ -307,10 +307,10 @@ module VX_dmem_controller (
.snp_req_full (vx_gpu_icache_snp_req.snp_req_full), .snp_req_full (vx_gpu_icache_snp_req.snp_req_full),
// Snoop Forward // Snoop Forward
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.snp_fwd_valid (), .snp_fwd_valid (),
.snp_fwd_addr (), .snp_fwd_addr (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
.snp_fwd_full (0) .snp_fwd_full (0)
); );

14
hw/rtl/VX_execute_unit.v
View File

@@ -4,15 +4,15 @@ module VX_execute_unit (
input wire clk, input wire clk,
input wire reset, input wire reset,
// Request // Request
VX_exec_unit_req_inter vx_exec_unit_req, VX_exec_unit_req_if vx_exec_unit_req,
// Output // Output
// Writeback // Writeback
VX_inst_exec_wb_inter vx_inst_exec_wb, VX_inst_exec_wb_if vx_inst_exec_wb,
// JAL Response // JAL Response
VX_jal_response_inter vx_jal_rsp, VX_jal_response_if vx_jal_rsp,
// Branch Response // Branch Response
VX_branch_response_inter vx_branch_rsp, VX_branch_response_if vx_branch_rsp,
input wire no_slot_exec, input wire no_slot_exec,
output wire out_delay output wire out_delay
@@ -109,11 +109,11 @@ module VX_execute_unit (
endgenerate endgenerate
// VX_inst_exec_wb_inter vx_inst_exec_wb_temp(); // VX_inst_exec_wb_if vx_inst_exec_wb_temp();
// JAL Response // JAL Response
VX_jal_response_inter vx_jal_rsp_temp(); VX_jal_response_if vx_jal_rsp_temp();
// Branch Response // Branch Response
VX_branch_response_inter vx_branch_rsp_temp(); VX_branch_response_if vx_branch_rsp_temp();
// Actual Writeback // Actual Writeback
assign vx_inst_exec_wb.rd = vx_exec_unit_req.rd; assign vx_inst_exec_wb.rd = vx_exec_unit_req.rd;

12
hw/rtl/VX_fetch.v
View File

@@ -3,18 +3,18 @@
module VX_fetch ( module VX_fetch (
input wire clk, input wire clk,
input wire reset, input wire reset,
VX_wstall_inter vx_wstall, VX_wstall_if vx_wstall,
VX_join_inter vx_join, VX_join_if vx_join,
input wire schedule_delay, input wire schedule_delay,
input wire icache_stage_delay, input wire icache_stage_delay,
input wire[`NW_BITS-1:0] icache_stage_wid, input wire[`NW_BITS-1:0] icache_stage_wid,
input wire[`NUM_THREADS-1:0] icache_stage_valids, input wire[`NUM_THREADS-1:0] icache_stage_valids,
output wire out_ebreak, output wire out_ebreak,
VX_jal_response_inter vx_jal_rsp, VX_jal_response_if vx_jal_rsp,
VX_branch_response_inter vx_branch_rsp, VX_branch_response_if vx_branch_rsp,
VX_inst_meta_inter fe_inst_meta_fi, VX_inst_meta_if fe_inst_meta_fi,
VX_warp_ctl_inter vx_warp_ctl VX_warp_ctl_if vx_warp_ctl
); );
wire[`NUM_THREADS-1:0] thread_mask; wire[`NUM_THREADS-1:0] thread_mask;

26
hw/rtl/VX_front_end.v
View File

@@ -6,26 +6,26 @@ module VX_front_end (
input wire schedule_delay, input wire schedule_delay,
VX_warp_ctl_inter vx_warp_ctl, VX_warp_ctl_if vx_warp_ctl,
VX_gpu_dcache_rsp_inter vx_icache_rsp, VX_gpu_dcache_rsp_if vx_icache_rsp,
VX_gpu_dcache_req_inter vx_icache_req, VX_gpu_dcache_req_if vx_icache_req,
VX_jal_response_inter vx_jal_rsp, VX_jal_response_if vx_jal_rsp,
VX_branch_response_inter vx_branch_rsp, VX_branch_response_if vx_branch_rsp,
VX_frE_to_bckE_req_inter vx_bckE_req, VX_frE_to_bckE_req_if vx_bckE_req,
output wire fetch_ebreak output wire fetch_ebreak
); );
VX_inst_meta_inter fe_inst_meta_fi(); VX_inst_meta_if fe_inst_meta_fi();
VX_inst_meta_inter fe_inst_meta_fi2(); VX_inst_meta_if fe_inst_meta_fi2();
VX_inst_meta_inter fe_inst_meta_id(); VX_inst_meta_if fe_inst_meta_id();
VX_frE_to_bckE_req_inter vx_frE_to_bckE_req(); VX_frE_to_bckE_req_if vx_frE_to_bckE_req();
VX_inst_meta_inter fd_inst_meta_de(); VX_inst_meta_if fd_inst_meta_de();
wire total_freeze = schedule_delay; wire total_freeze = schedule_delay;
wire icache_stage_delay; wire icache_stage_delay;
@@ -48,8 +48,8 @@ end
assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak; assign fetch_ebreak = vortex_ebreak || terminate_sim || old_ebreak;
VX_wstall_inter vx_wstall(); VX_wstall_if vx_wstall();
VX_join_inter vx_join(); VX_join_if vx_join();
VX_fetch vx_fetch( VX_fetch vx_fetch(
.clk (clk), .clk (clk),

4
hw/rtl/VX_gpgpu_inst.v
View File

@@ -2,10 +2,10 @@
module VX_gpgpu_inst ( module VX_gpgpu_inst (
// Input // Input
VX_gpu_inst_req_inter vx_gpu_inst_req, VX_gpu_inst_req_if vx_gpu_inst_req,
// Output // Output
VX_warp_ctl_inter vx_warp_ctl VX_warp_ctl_if vx_warp_ctl
); );
wire[`NUM_THREADS-1:0] curr_valids = vx_gpu_inst_req.valid; wire[`NUM_THREADS-1:0] curr_valids = vx_gpu_inst_req.valid;
wire is_split = (vx_gpu_inst_req.is_split); wire is_split = (vx_gpu_inst_req.is_split);

32
hw/rtl/VX_gpr.v
View File

@@ -4,8 +4,8 @@ module VX_gpr (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire valid_write_request, input wire valid_write_request,
VX_gpr_read_inter vx_gpr_read, VX_gpr_read_if vx_gpr_read,
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_a_reg_data, output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_a_reg_data,
output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_b_reg_data output reg[`NUM_THREADS-1:0][`NUM_GPRS-1:0] out_b_reg_data
@@ -13,28 +13,28 @@ module VX_gpr (
wire write_enable; wire write_enable;
`ifndef ASIC `ifndef ASIC
assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)) && (vx_writeback_inter.rd != 0); assign write_enable = valid_write_request && ((vx_writeback_if.wb != 0)) && (vx_writeback_if.rd != 0);
byte_enabled_simple_dual_port_ram first_ram( byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable), .we (write_enable),
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.waddr (vx_writeback_inter.rd), .waddr (vx_writeback_if.rd),
.raddr1(vx_gpr_read.rs1), .raddr1(vx_gpr_read.rs1),
.raddr2(vx_gpr_read.rs2), .raddr2(vx_gpr_read.rs2),
.be (vx_writeback_inter.wb_valid), .be (vx_writeback_if.wb_valid),
.wdata (vx_writeback_inter.write_data), .wdata (vx_writeback_if.write_data),
.q1 (out_a_reg_data), .q1 (out_a_reg_data),
.q2 (out_b_reg_data) .q2 (out_b_reg_data)
); );
`else `else
assign write_enable = valid_write_request && ((vx_writeback_inter.wb != 0)); assign write_enable = valid_write_request && ((vx_writeback_if.wb != 0));
wire going_to_write = write_enable & (|vx_writeback_inter.wb_valid); wire going_to_write = write_enable & (|vx_writeback_if.wb_valid);
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask; wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] write_bit_mask;
genvar curr_t; genvar curr_t;
for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin
wire local_write = write_enable & vx_writeback_inter.wb_valid[curr_t]; wire local_write = write_enable & vx_writeback_if.wb_valid[curr_t];
assign write_bit_mask[curr_t] = {`NUM_GPRS{~local_write}}; assign write_bit_mask[curr_t] = {`NUM_GPRS{~local_write}};
end end
@@ -65,12 +65,12 @@ module VX_gpr (
assign out_b_reg_data = temp_b; assign out_b_reg_data = temp_b;
`endif `endif
wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (vx_writeback_inter.rd != 0) ? vx_writeback_inter.write_data : 0; wire[`NUM_THREADS-1:0][`NUM_GPRS-1:0] to_write = (vx_writeback_if.rd != 0) ? vx_writeback_if.write_data : 0;
genvar curr_base_thread; genvar curr_base_thread;
for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4) for (curr_base_thread = 0; curr_base_thread < 'NT; curr_base_thread=curr_base_thread+4)
begin begin
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
rf2_32x128_wm1 first_ram ( rf2_32x128_wm1 first_ram (
.CENYA(), .CENYA(),
.AYA(), .AYA(),
@@ -86,7 +86,7 @@ module VX_gpr (
.CLKB(clk), .CLKB(clk),
.CENB(cenb), .CENB(cenb),
.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
.AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), .AB(vx_writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]),
.DB(to_write[(curr_base_thread+3):(curr_base_thread)]), .DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
.EMAA(3'b011), .EMAA(3'b011),
.EMASA(1'b0), .EMASA(1'b0),
@@ -107,9 +107,9 @@ module VX_gpr (
.SEB(1'b0), .SEB(1'b0),
.COLLDISN(1'b1) .COLLDISN(1'b1)
); );
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
rf2_`NUM_GPRSx128_wm1 second_ram ( rf2_`NUM_GPRSx128_wm1 second_ram (
.CENYA(), .CENYA(),
.AYA(), .AYA(),
@@ -125,7 +125,7 @@ module VX_gpr (
.CLKB(clk), .CLKB(clk),
.CENB(cenb), .CENB(cenb),
.WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]), .WENB(write_bit_mask[(curr_base_thread+3):(curr_base_thread)]),
.AB(vx_writeback_inter.rd[(curr_base_thread+3):(curr_base_thread)]), .AB(vx_writeback_if.rd[(curr_base_thread+3):(curr_base_thread)]),
.DB(to_write[(curr_base_thread+3):(curr_base_thread)]), .DB(to_write[(curr_base_thread+3):(curr_base_thread)]),
.EMAA(3'b011), .EMAA(3'b011),
.EMASA(1'b0), .EMASA(1'b0),
@@ -146,7 +146,7 @@ module VX_gpr (
.SEB(1'b0), .SEB(1'b0),
.COLLDISN(1'b1) .COLLDISN(1'b1)
); );
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
end end
`endif `endif

30
hw/rtl/VX_gpr_stage.v
View File

@@ -12,16 +12,16 @@ module VX_gpr_stage (
// inputs // inputs
// Instruction Information // Instruction Information
VX_frE_to_bckE_req_inter vx_bckE_req, VX_frE_to_bckE_req_if vx_bckE_req,
// WriteBack inputs // WriteBack inputs
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
// Outputs // Outputs
VX_exec_unit_req_inter vx_exec_unit_req, VX_exec_unit_req_if vx_exec_unit_req,
VX_lsu_req_inter vx_lsu_req, VX_lsu_req_if vx_lsu_req,
VX_gpu_inst_req_inter vx_gpu_inst_req, VX_gpu_inst_req_if vx_gpu_inst_req,
VX_csr_req_inter vx_csr_req VX_csr_req_if vx_csr_req
); );
`DEBUG_BEGIN `DEBUG_BEGIN
wire[31:0] curr_PC = vx_bckE_req.curr_PC; wire[31:0] curr_PC = vx_bckE_req.curr_PC;
@@ -31,27 +31,27 @@ module VX_gpr_stage (
wire jalQual = vx_bckE_req.jalQual; wire jalQual = vx_bckE_req.jalQual;
`DEBUG_END `DEBUG_END
VX_gpr_read_inter vx_gpr_read(); VX_gpr_read_if vx_gpr_read();
assign vx_gpr_read.rs1 = vx_bckE_req.rs1; assign vx_gpr_read.rs1 = vx_bckE_req.rs1;
assign vx_gpr_read.rs2 = vx_bckE_req.rs2; assign vx_gpr_read.rs2 = vx_bckE_req.rs2;
assign vx_gpr_read.warp_num = vx_bckE_req.warp_num; assign vx_gpr_read.warp_num = vx_bckE_req.warp_num;
`ifndef ASIC `ifndef ASIC
VX_gpr_jal_inter vx_gpr_jal(); VX_gpr_jal_if vx_gpr_jal();
assign vx_gpr_jal.is_jal = vx_bckE_req.jalQual; assign vx_gpr_jal.is_jal = vx_bckE_req.jalQual;
assign vx_gpr_jal.curr_PC = vx_bckE_req.curr_PC; assign vx_gpr_jal.curr_PC = vx_bckE_req.curr_PC;
`else `else
VX_gpr_jal_inter vx_gpr_jal(); VX_gpr_jal_if vx_gpr_jal();
assign vx_gpr_jal.is_jal = vx_exec_unit_req.jalQual; assign vx_gpr_jal.is_jal = vx_exec_unit_req.jalQual;
assign vx_gpr_jal.curr_PC = vx_exec_unit_req.curr_PC; assign vx_gpr_jal.curr_PC = vx_exec_unit_req.curr_PC;
`endif `endif
VX_gpr_data_inter vx_gpr_datf(); VX_gpr_data_if vx_gpr_datf();
VX_gpr_wrapper vx_grp_wrapper ( VX_gpr_wrapper vx_grp_wrapper (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.vx_writeback_inter(vx_writeback_inter), .vx_writeback_if(vx_writeback_if),
.vx_gpr_read (vx_gpr_read), .vx_gpr_read (vx_gpr_read),
.vx_gpr_jal (vx_gpr_jal), .vx_gpr_jal (vx_gpr_jal),
@@ -63,10 +63,10 @@ module VX_gpr_stage (
// assign vx_bckE_req_out.csr_mask = (vx_bckE_req.sr_immed == 1'b1) ? {27'h0, vx_bckE_req.rs1} : vx_gpr_data.a_reg_data[0]; // assign vx_bckE_req_out.csr_mask = (vx_bckE_req.sr_immed == 1'b1) ? {27'h0, vx_bckE_req.rs1} : vx_gpr_data.a_reg_data[0];
// Outputs // Outputs
VX_exec_unit_req_inter vx_exec_unit_req_temp(); VX_exec_unit_req_if vx_exec_unit_req_temp();
VX_lsu_req_inter vx_lsu_req_temp(); VX_lsu_req_if vx_lsu_req_temp();
VX_gpu_inst_req_inter vx_gpu_inst_req_temp(); VX_gpu_inst_req_if vx_gpu_inst_req_temp();
VX_csr_req_inter vx_csr_req_temp(); VX_csr_req_if vx_csr_req_temp();
VX_inst_multiplex vx_inst_mult( VX_inst_multiplex vx_inst_mult(
.vx_bckE_req (vx_bckE_req), .vx_bckE_req (vx_bckE_req),

10
hw/rtl/VX_gpr_wrapper.v
View File

@@ -3,9 +3,9 @@
module VX_gpr_wrapper ( module VX_gpr_wrapper (
input wire clk, input wire clk,
input wire reset, input wire reset,
VX_gpr_read_inter vx_gpr_read, VX_gpr_read_if vx_gpr_read,
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
VX_gpr_jal_inter vx_gpr_jal, VX_gpr_jal_if vx_gpr_jal,
output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data, output wire[`NUM_THREADS-1:0][31:0] out_a_reg_data,
output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data output wire[`NUM_THREADS-1:0][31:0] out_b_reg_data
@@ -52,13 +52,13 @@ module VX_gpr_wrapper (
for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs
wire valid_write_request = warp_index == vx_writeback_inter.wb_warp_num; wire valid_write_request = warp_index == vx_writeback_if.wb_warp_num;
VX_gpr vx_gpr( VX_gpr vx_gpr(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.valid_write_request(valid_write_request), .valid_write_request(valid_write_request),
.vx_gpr_read (vx_gpr_read), .vx_gpr_read (vx_gpr_read),
.vx_writeback_inter (vx_writeback_inter), .vx_writeback_if (vx_writeback_if),
.out_a_reg_data (temp_a_reg_data[warp_index]), .out_a_reg_data (temp_a_reg_data[warp_index]),
.out_b_reg_data (temp_b_reg_data[warp_index]) .out_b_reg_data (temp_b_reg_data[warp_index])
); );

8
hw/rtl/VX_icache_stage.v
View File

@@ -7,11 +7,11 @@ module VX_icache_stage (
output wire icache_stage_delay, output wire icache_stage_delay,
output wire[`NW_BITS-1:0] icache_stage_wid, output wire[`NW_BITS-1:0] icache_stage_wid,
output wire[`NUM_THREADS-1:0] icache_stage_valids, output wire[`NUM_THREADS-1:0] icache_stage_valids,
VX_inst_meta_inter fe_inst_meta_fi, VX_inst_meta_if fe_inst_meta_fi,
VX_inst_meta_inter fe_inst_meta_id, VX_inst_meta_if fe_inst_meta_id,
VX_gpu_dcache_rsp_inter vx_icache_rsp, VX_gpu_dcache_rsp_if vx_icache_rsp,
VX_gpu_dcache_req_inter vx_icache_req VX_gpu_dcache_req_if vx_icache_req
); );
reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0]; reg[`NUM_THREADS-1:0] threads_active[`NUM_WARPS-1:0];

12
hw/rtl/VX_inst_multiplex.v
View File

@@ -2,14 +2,14 @@
module VX_inst_multiplex ( module VX_inst_multiplex (
// Inputs // Inputs
VX_frE_to_bckE_req_inter vx_bckE_req, VX_frE_to_bckE_req_if vx_bckE_req,
VX_gpr_data_inter vx_gpr_data, VX_gpr_data_if vx_gpr_data,
// Outputs // Outputs
VX_exec_unit_req_inter vx_exec_unit_req, VX_exec_unit_req_if vx_exec_unit_req,
VX_lsu_req_inter vx_lsu_req, VX_lsu_req_if vx_lsu_req,
VX_gpu_inst_req_inter vx_gpu_inst_req, VX_gpu_inst_req_if vx_gpu_inst_req,
VX_csr_req_inter vx_csr_req VX_csr_req_if vx_csr_req
); );
wire[`NUM_THREADS-1:0] is_mem_mask; wire[`NUM_THREADS-1:0] is_mem_mask;

8
hw/rtl/VX_lsu.v
View File

@@ -4,13 +4,13 @@ module VX_lsu (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire no_slot_mem, input wire no_slot_mem,
VX_lsu_req_inter vx_lsu_req, VX_lsu_req_if vx_lsu_req,
// Write back to GPR // Write back to GPR
VX_inst_mem_wb_inter vx_mem_wb, VX_inst_mem_wb_if vx_mem_wb,
VX_gpu_dcache_rsp_inter vx_dcache_rsp, VX_gpu_dcache_rsp_if vx_dcache_rsp,
VX_gpu_dcache_req_inter vx_dcache_req, VX_gpu_dcache_req_if vx_dcache_req,
output wire out_delay output wire out_delay
); );
// Generate Addresses // Generate Addresses

10
hw/rtl/VX_scheduler.v
View File

@@ -6,8 +6,8 @@ module VX_scheduler (
input wire memory_delay, input wire memory_delay,
input wire exec_delay, input wire exec_delay,
input wire gpr_stage_delay, input wire gpr_stage_delay,
VX_frE_to_bckE_req_inter vx_bckE_req, VX_frE_to_bckE_req_if vx_bckE_req,
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
output wire schedule_delay, output wire schedule_delay,
output wire is_empty output wire is_empty
@@ -18,7 +18,7 @@ module VX_scheduler (
reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0]; reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
wire valid_wb = (vx_writeback_inter.wb != 0) && (|vx_writeback_inter.wb_valid) && (vx_writeback_inter.rd != 0); wire valid_wb = (vx_writeback_if.wb != 0) && (|vx_writeback_if.wb_valid) && (vx_writeback_if.rd != 0);
wire wb_inc = (vx_bckE_req.wb != 0) && (vx_bckE_req.rd != 0); wire wb_inc = (vx_bckE_req.wb != 0) && (vx_bckE_req.rd != 0);
wire rs1_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rs1] != 0; wire rs1_rename = rename_table[vx_bckE_req.warp_num][vx_bckE_req.rs1] != 0;
@@ -59,7 +59,7 @@ module VX_scheduler (
end end
end else begin end else begin
if (valid_wb) begin if (valid_wb) begin
rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] <= rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & (~vx_writeback_inter.wb_valid); rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] <= rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] & (~vx_writeback_if.wb_valid);
end end
if (!schedule_delay && wb_inc) begin if (!schedule_delay && wb_inc) begin
@@ -67,7 +67,7 @@ module VX_scheduler (
end end
if (valid_wb if (valid_wb
&& (0 == (rename_table[vx_writeback_inter.wb_warp_num][vx_writeback_inter.rd] & ~vx_writeback_inter.wb_valid))) begin && (0 == (rename_table[vx_writeback_if.wb_warp_num][vx_writeback_if.rd] & ~vx_writeback_if.wb_valid))) begin
count_valid <= count_valid - 1; count_valid <= count_valid - 1;
end end

16
hw/rtl/VX_writeback.v
View File

@@ -4,20 +4,20 @@ module VX_writeback (
input wire clk, input wire clk,
input wire reset, input wire reset,
// Mem WB info // Mem WB info
VX_inst_mem_wb_inter vx_mem_wb, VX_inst_mem_wb_if vx_mem_wb,
// EXEC Unit WB info // EXEC Unit WB info
VX_inst_exec_wb_inter vx_inst_exec_wb, VX_inst_exec_wb_if vx_inst_exec_wb,
// CSR Unit WB info // CSR Unit WB info
VX_csr_wb_inter vx_csr_wb, VX_csr_wb_if vx_csr_wb,
// Actual WB to GPR // Actual WB to GPR
VX_wb_inter vx_writeback_inter, VX_wb_if vx_writeback_if,
output wire no_slot_mem, output wire no_slot_mem,
output wire no_slot_exec, output wire no_slot_exec,
output wire no_slot_csr output wire no_slot_csr
); );
VX_wb_inter vx_writeback_tempp(); VX_wb_if vx_writeback_tempp();
wire exec_wb = (vx_inst_exec_wb.wb != 0) && (|vx_inst_exec_wb.wb_valid); wire exec_wb = (vx_inst_exec_wb.wb != 0) && (|vx_inst_exec_wb.wb_valid);
wire mem_wb = (vx_mem_wb.wb != 0) && (|vx_mem_wb.wb_valid); wire mem_wb = (vx_mem_wb.wb != 0) && (|vx_mem_wb.wb_valid);
@@ -72,18 +72,18 @@ module VX_writeback (
.stall(zero), .stall(zero),
.flush(zero), .flush(zero),
.in ({vx_writeback_tempp.write_data, vx_writeback_tempp.wb_valid, vx_writeback_tempp.rd, vx_writeback_tempp.wb, vx_writeback_tempp.wb_warp_num, vx_writeback_tempp.wb_pc}), .in ({vx_writeback_tempp.write_data, vx_writeback_tempp.wb_valid, vx_writeback_tempp.rd, vx_writeback_tempp.wb, vx_writeback_tempp.wb_warp_num, vx_writeback_tempp.wb_pc}),
.out ({use_wb_data , vx_writeback_inter.wb_valid, vx_writeback_inter.rd, vx_writeback_inter.wb, vx_writeback_inter.wb_warp_num, vx_writeback_inter.wb_pc}) .out ({use_wb_data , vx_writeback_if.wb_valid, vx_writeback_if.rd, vx_writeback_if.wb, vx_writeback_if.wb_warp_num, vx_writeback_if.wb_pc})
); );
reg[31:0] last_data_wb /* verilator public */ ; reg[31:0] last_data_wb /* verilator public */ ;
always @(posedge clk) begin always @(posedge clk) begin
if ((|vx_writeback_inter.wb_valid) && (vx_writeback_inter.wb != 0) && (vx_writeback_inter.rd == 28)) begin if ((|vx_writeback_if.wb_valid) && (vx_writeback_if.wb != 0) && (vx_writeback_if.rd == 28)) begin
last_data_wb <= use_wb_data[0]; last_data_wb <= use_wb_data[0];
end end
end end
assign vx_writeback_inter.write_data = use_wb_data; assign vx_writeback_if.write_data = use_wb_data;
endmodule : VX_writeback endmodule : VX_writeback

40
hw/rtl/Vortex.v
View File

@@ -99,12 +99,12 @@ module Vortex
wire schedule_delay; wire schedule_delay;
// Dcache Interface // Dcache Interface
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp(); VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_rsp();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req(); VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual(); VX_gpu_dcache_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) vx_dcache_req_qual();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req(); VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_req();
VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res(); VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) vx_gpu_dcache_dram_res();
assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid; assign vx_gpu_dcache_dram_res.dram_rsp_valid = dram_rsp_valid;
assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr; assign vx_gpu_dcache_dram_res.dram_rsp_addr = dram_rsp_addr;
@@ -144,11 +144,11 @@ module Vortex
assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc; assign vx_dcache_req_qual.core_req_pc = vx_dcache_req.core_req_pc;
assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot; assign vx_dcache_req_qual.core_no_wb_slot = vx_dcache_req.core_no_wb_slot;
VX_gpu_dcache_rsp_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp(); VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_rsp();
VX_gpu_dcache_req_inter #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req(); VX_gpu_dcache_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) vx_icache_req();
VX_gpu_dcache_dram_req_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req(); VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_req();
VX_gpu_dcache_dram_rsp_inter #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res(); VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) vx_gpu_icache_dram_res();
assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid; assign vx_gpu_icache_dram_res.dram_rsp_valid = I_dram_rsp_valid;
assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr; assign vx_gpu_icache_dram_res.dram_rsp_addr = I_dram_rsp_addr;
@@ -171,19 +171,19 @@ module Vortex
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// Front-end to Back-end // Front-end to Back-end
VX_frE_to_bckE_req_inter vx_bckE_req(); // New instruction request to EXE/MEM VX_frE_to_bckE_req_if vx_bckE_req(); // New instruction request to EXE/MEM
// Back-end to Front-end // Back-end to Front-end
VX_wb_inter vx_writeback_inter(); // Writeback to GPRs VX_wb_if vx_writeback_if(); // Writeback to GPRs
VX_branch_response_inter vx_branch_rsp(); // Branch Resolution to Fetch VX_branch_response_if vx_branch_rsp(); // Branch Resolution to Fetch
VX_jal_response_inter vx_jal_rsp(); // Jump resolution to Fetch VX_jal_response_if vx_jal_rsp(); // Jump resolution to Fetch
// CSR Buses // CSR Buses
// VX_csr_write_request_inter vx_csr_w_req(); // VX_csr_write_request_if vx_csr_w_req();
VX_warp_ctl_inter vx_warp_ctl(); VX_warp_ctl_if vx_warp_ctl();
VX_gpu_snp_req_rsp vx_gpu_icache_snp_req(); VX_gpu_snp_req_rsp_if vx_gpu_icache_snp_req();
VX_gpu_snp_req_rsp vx_gpu_dcache_snp_req(); VX_gpu_snp_req_rsp_if vx_gpu_dcache_snp_req();
assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid; assign vx_gpu_dcache_snp_req.snp_req_valid = snp_req_valid;
assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr; assign vx_gpu_dcache_snp_req.snp_req_addr = snp_req_addr;
@@ -209,7 +209,7 @@ VX_scheduler schedule(
.exec_delay (exec_delay), .exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay), .gpr_stage_delay (gpr_stage_delay),
.vx_bckE_req (vx_bckE_req), .vx_bckE_req (vx_bckE_req),
.vx_writeback_inter (vx_writeback_inter), .vx_writeback_if (vx_writeback_if),
.schedule_delay (schedule_delay), .schedule_delay (schedule_delay),
.is_empty (scheduler_empty) .is_empty (scheduler_empty)
); );
@@ -224,7 +224,7 @@ VX_back_end #(.CORE_ID(CORE_ID)) vx_back_end(
.vx_branch_rsp (vx_branch_rsp), .vx_branch_rsp (vx_branch_rsp),
.vx_dcache_rsp (vx_dcache_rsp), .vx_dcache_rsp (vx_dcache_rsp),
.vx_dcache_req (vx_dcache_req), .vx_dcache_req (vx_dcache_req),
.vx_writeback_inter (vx_writeback_inter), .vx_writeback_if (vx_writeback_if),
.out_mem_delay (memory_delay), .out_mem_delay (memory_delay),
.out_exec_delay (exec_delay), .out_exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay) .gpr_stage_delay (gpr_stage_delay)
@@ -257,7 +257,7 @@ VX_dmem_controller vx_dmem_controller(
// .clk (clk), // .clk (clk),
// .in_decode_csr_address(decode_csr_address), // .in_decode_csr_address(decode_csr_address),
// .vx_csr_w_req (vx_csr_w_req), // .vx_csr_w_req (vx_csr_w_req),
// .in_wb_valid (vx_writeback_inter.wb_valid[0]), // .in_wb_valid (vx_writeback_if.wb_valid[0]),
// .out_decode_csr_data (csr_decode_csr_data) // .out_decode_csr_data (csr_decode_csr_data)
// ); // );

4
hw/rtl/Vortex_Cluster.v
View File

@@ -227,12 +227,12 @@ module Vortex_Cluster
// Core Writeback // Core Writeback
.core_wb_valid (l2c_wb), .core_wb_valid (l2c_wb),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.core_wb_req_rd (), .core_wb_req_rd (),
.core_wb_req_wb (), .core_wb_req_wb (),
.core_wb_warp_num (), .core_wb_warp_num (),
.core_wb_pc (), .core_wb_pc (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
.core_wb_readdata ({l2c_wb_data}), .core_wb_readdata ({l2c_wb_data}),
.core_wb_address (l2c_wb_addr), .core_wb_address (l2c_wb_addr),

4
hw/rtl/Vortex_Socket.v
View File

@@ -225,12 +225,12 @@ module Vortex_Socket (
// Core Writeback // Core Writeback
.core_wb_valid (l3c_wb), .core_wb_valid (l3c_wb),
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
.core_wb_req_rd (), .core_wb_req_rd (),
.core_wb_req_wb (), .core_wb_req_wb (),
.core_wb_warp_num (), .core_wb_warp_num (),
.core_wb_pc (), .core_wb_pc (),
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
.core_wb_readdata ({l3c_wb_data}), .core_wb_readdata ({l3c_wb_data}),
.core_wb_address (l3c_wb_addr), .core_wb_address (l3c_wb_addr),

8
hw/rtl/cache/VX_cache_data.v vendored
View File

@@ -104,7 +104,7 @@ module VX_cache_data #(
assign data_use = data_out_d; assign data_use = data_out_d;
// Using ASIC MEM // Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
rf2_32x128_wm1 data ( rf2_32x128_wm1 data (
.CENYA(), .CENYA(),
.AYA(), .AYA(),
@@ -141,7 +141,7 @@ module VX_cache_data #(
.SEB(1'b0), .SEB(1'b0),
.COLLDISN(1'b1) .COLLDISN(1'b1)
); );
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
wire[16:0] old_tag; wire[16:0] old_tag;
wire old_valid; wire old_valid;
@@ -169,7 +169,7 @@ module VX_cache_data #(
assign valid_use = old_valid; assign valid_use = old_valid;
assign tag_use = old_tag; assign tag_use = old_tag;
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
rf2_32x19_wm0 meta ( rf2_32x19_wm0 meta (
.CENYA(), .CENYA(),
.AYA(), .AYA(),
@@ -206,7 +206,7 @@ module VX_cache_data #(
.SEB(1'b0), .SEB(1'b0),
.COLLDISN(1'b1) .COLLDISN(1'b1)
); );
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
`endif `endif
endmodule endmodule

42
hw/rtl/cache/VX_d_cache_encapsulate.v vendored
View File

@@ -53,32 +53,32 @@ module VX_d_cache_encapsulate (
// Inter // Inter
wire [`NUM_THREADS-1:0] i_p_valid_inter; wire [`NUM_THREADS-1:0] i_p_valid_if;
wire [`NUM_THREADS-1:0][31:0] i_p_addr_inter; wire [`NUM_THREADS-1:0][31:0] i_p_addr_if;
wire [`NUM_THREADS-1:0][31:0] i_p_writedata_inter; wire [`NUM_THREADS-1:0][31:0] i_p_writedata_if;
reg [`NUM_THREADS-1:0][31:0] o_p_readdata_inter; reg [`NUM_THREADS-1:0][31:0] o_p_readdata_if;
reg [`NUM_THREADS-1:0] o_p_readdata_valid_inter; reg [`NUM_THREADS-1:0] o_p_readdata_valid_if;
reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter; reg[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_if;
wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter; wire[NUM_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_if;
genvar curr_thraed, curr_bank, curr_word; genvar curr_thraed, curr_bank, curr_word;
generate generate
for (curr_thraed = 0; curr_thraed < `NUM_THREADS; curr_thraed = curr_thraed + 1) begin : threads for (curr_thraed = 0; curr_thraed < `NUM_THREADS; curr_thraed = curr_thraed + 1) begin : threads
assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed]; assign i_p_valid_if[curr_thraed] = i_p_valid[curr_thraed];
assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed]; assign i_p_addr_if[curr_thraed] = i_p_addr[curr_thraed];
assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed]; assign i_p_writedata_if[curr_thraed] = i_p_writedata[curr_thraed];
assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed]; assign o_p_readdata[curr_thraed] = o_p_readdata_if[curr_thraed];
assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed]; assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_if[curr_thraed];
end end
for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank = curr_bank + 1) begin : banks for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank = curr_bank + 1) begin : banks
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words
assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word]; assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_if[curr_bank][curr_word];
assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word]; assign i_m_readdata_if[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
end end
end end
@@ -87,19 +87,19 @@ module VX_d_cache_encapsulate (
VX_d_cache dcache( VX_d_cache dcache(
.clk (clk), .clk (clk),
.rst (rst), .rst (rst),
.i_p_valid (i_p_valid_inter), .i_p_valid (i_p_valid_if),
.i_p_addr (i_p_addr_inter), .i_p_addr (i_p_addr_if),
.i_p_initial_request(i_p_initial_request), .i_p_initial_request(i_p_initial_request),
.i_p_writedata (i_p_writedata_inter), .i_p_writedata (i_p_writedata_if),
.i_p_read_or_write (i_p_read_or_write), .i_p_read_or_write (i_p_read_or_write),
.o_p_readdata (o_p_readdata_inter), .o_p_readdata (o_p_readdata_if),
.o_p_readdata_valid (o_p_readdata_valid_inter), .o_p_readdata_valid (o_p_readdata_valid_if),
.o_p_waitrequest (o_p_waitrequest), .o_p_waitrequest (o_p_waitrequest),
.o_m_addr (o_m_addr), .o_m_addr (o_m_addr),
.o_m_valid (o_m_valid), .o_m_valid (o_m_valid),
.o_m_writedata (o_m_writedata_inter), .o_m_writedata (o_m_writedata_if),
.o_m_read_or_write (o_m_read_or_write), .o_m_read_or_write (o_m_read_or_write),
.i_m_readdata (i_m_readdata_inter), .i_m_readdata (i_m_readdata_if),
.i_m_ready (i_m_ready) .i_m_ready (i_m_ready)
); );

6
hw/rtl/compat/VX_divide.v
View File

@@ -25,9 +25,9 @@ module VX_divide #(
generate generate
if (NREP != DREP) begin if (NREP != DREP) begin
/* verilator lint_off DECLFILENAME */ `IGNORE_WARNINGS_BEGIN
different_nrep_drep_not_yet_supported non_existing_module(); different_nrep_drep_not_yet_supported non_existing_module();
/* verilator lint_on DECLFILENAME */ `IGNORE_WARNINGS_END
end end
if (IMPL == "quartus") begin if (IMPL == "quartus") begin
@@ -98,7 +98,7 @@ module VX_divide #(
if (NREP == "SIGNED") begin if (NREP == "SIGNED") begin
/*VX_divide_internal_signed #( /*VX_divide_ifnal_signed #(
.WIDTHN, .WIDTHN,
.WIDTHD .WIDTHD
)div( )div(

4
hw/rtl/compat/VX_mult.v
View File

@@ -30,7 +30,7 @@ module VX_mult #(
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5; localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
if (FORCE_LE == "YES") begin if (FORCE_LE == "YES") begin
/* verilator lint_off DECLFILENAME */ `IGNORE_WARNINGS_BEGIN
lpm_mult #( lpm_mult #(
.LPM_WIDTHA(WIDTHA), .LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB), .LPM_WIDTHB(WIDTHB),
@@ -47,7 +47,7 @@ module VX_mult #(
.datab(datab), .datab(datab),
.result(result) .result(result)
); );
/* verilator lint_on DECLFILENAME */ `IGNORE_WARNINGS_END
end end
else begin else begin
lpm_mult#( lpm_mult#(

2
hw/rtl/interfaces/VX_branch_response_inter.v → hw/rtl/interfaces/VX_branch_response_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_branch_response_inter (); interface VX_branch_response_if ();
wire valid_branch; wire valid_branch;
wire branch_dir; wire branch_dir;

2
hw/rtl/interfaces/VX_csr_req_inter.v → hw/rtl/interfaces/VX_csr_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_csr_req_inter (); interface VX_csr_req_if ();
wire [`NUM_THREADS-1:0] valid; wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num; wire [`NW_BITS-1:0] warp_num;

2
hw/rtl/interfaces/VX_csr_wb_inter.v → hw/rtl/interfaces/VX_csr_wb_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_csr_wb_inter (); interface VX_csr_wb_if ();
wire [`NUM_THREADS-1:0] valid; wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num; wire [`NW_BITS-1:0] warp_num;

2
hw/rtl/interfaces/VX_dcache_request_inter.v → hw/rtl/interfaces/VX_dcache_request_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_dcache_request_inter (); interface VX_dcache_request_if ();
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address; wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire [2:0] out_cache_driver_in_mem_read; wire [2:0] out_cache_driver_in_mem_read;

2
hw/rtl/interfaces/VX_dcache_response_inter.v → hw/rtl/interfaces/VX_dcache_response_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_dcache_response_inter (); interface VX_dcache_response_if ();
wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data; wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay; wire delay;

2
hw/rtl/interfaces/VX_dram_req_rsp_inter.v → hw/rtl/interfaces/VX_dram_req_rsp_if.v
View File

@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_dram_req_rsp_inter #( interface VX_dram_req_rsp_if #(
parameter NUM_BANKS = 8, parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4 parameter NUM_WORDS_PER_BLOCK = 4
) (); ) ();

2
hw/rtl/interfaces/VX_exec_unit_req_inter.v → hw/rtl/interfaces/VX_exec_unit_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_exec_unit_req_inter (); interface VX_exec_unit_req_if ();
// Meta // Meta
wire [`NUM_THREADS-1:0] valid; wire [`NUM_THREADS-1:0] valid;

2
hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v → hw/rtl/interfaces/VX_frE_to_bckE_req_if.v
View File

@@ -3,7 +3,7 @@
`include "VX_define.vh" `include "VX_define.vh"
interface VX_frE_to_bckE_req_inter (); interface VX_frE_to_bckE_req_if ();
wire [11:0] csr_address; wire [11:0] csr_address;
wire is_csr; wire is_csr;

2
hw/rtl/interfaces/VX_gpr_data_inter.v → hw/rtl/interfaces/VX_gpr_data_if.v
View File

@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_gpr_data_inter (); interface VX_gpr_data_if ();
wire [`NUM_THREADS-1:0][31:0] a_reg_data; wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data; wire [`NUM_THREADS-1:0][31:0] b_reg_data;

2
hw/rtl/interfaces/VX_gpr_jal_inter.v → hw/rtl/interfaces/VX_gpr_jal_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_gpr_jal_inter (); interface VX_gpr_jal_if ();
wire is_jal; wire is_jal;
wire[31:0] curr_PC; wire[31:0] curr_PC;

2
hw/rtl/interfaces/VX_gpr_read_inter.v → hw/rtl/interfaces/VX_gpr_read_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_gpr_read_inter (); interface VX_gpr_read_if ();
wire [4:0] rs1; wire [4:0] rs1;
wire [4:0] rs2; wire [4:0] rs2;

2
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v → hw/rtl/interfaces/VX_gpu_dcache_dram_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_inter #( interface VX_gpu_dcache_dram_req_if #(
parameter BANK_LINE_WORDS = 2 parameter BANK_LINE_WORDS = 2
) (); ) ();

2
hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v → hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_rsp_inter #( interface VX_gpu_dcache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2 parameter BANK_LINE_WORDS = 2
) (); ) ();
// DRAM Response // DRAM Response

2
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v → hw/rtl/interfaces/VX_gpu_dcache_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_req_inter #( interface VX_gpu_dcache_req_if #(
parameter NUM_REQUESTS = 32 parameter NUM_REQUESTS = 32
) (); ) ();

2
hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v → hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_rsp_inter #( interface VX_gpu_dcache_rsp_if #(
parameter NUM_REQUESTS = 32 parameter NUM_REQUESTS = 32
) (); ) ();

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v → hw/rtl/interfaces/VX_gpu_dcache_snp_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_snp_req_inter (); interface VX_gpu_dcache_snp_req_if ();
// Snoop Req // Snoop Req
wire snp_req_valid; wire snp_req_valid;
wire [31:0] snp_req_addr; wire [31:0] snp_req_addr;

2
hw/rtl/interfaces/VX_gpu_inst_req_inter.v → hw/rtl/interfaces/VX_gpu_inst_req_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_gpu_inst_req_inter(); interface VX_gpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid; wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num; wire [`NW_BITS-1:0] warp_num;

2
hw/rtl/interfaces/VX_gpu_snp_req_rsp.v → hw/rtl/interfaces/VX_gpu_snp_req_rsp_if.v
View File

@@ -3,7 +3,7 @@
`include "../generic_cache/VX_cache_config.vh" `include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_snp_req_rsp (); interface VX_gpu_snp_req_rsp_if ();
// Snoop request // Snoop request
wire snp_req_valid; wire snp_req_valid;

2
hw/rtl/interfaces/VX_icache_request_inter.v → hw/rtl/interfaces/VX_icache_request_if.v
View File

@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_icache_request_inter (); interface VX_icache_request_if ();
wire [31:0] pc_address; wire [31:0] pc_address;
wire [2:0] out_cache_driver_in_mem_read; wire [2:0] out_cache_driver_in_mem_read;

2
hw/rtl/interfaces/VX_icache_response_inter.v → hw/rtl/interfaces/VX_icache_response_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_icache_response_inter (); interface VX_icache_response_if ();
// wire ready; // wire ready;
// wire stall; // wire stall;

2
hw/rtl/interfaces/VX_inst_exec_wb_inter.v → hw/rtl/interfaces/VX_inst_exec_wb_if.v
View File

@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_inst_exec_wb_inter (); interface VX_inst_exec_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc; wire [31:0] exec_wb_pc;

2
hw/rtl/interfaces/VX_inst_mem_wb_inter.v → hw/rtl/interfaces/VX_inst_mem_wb_if.v
View File

@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_inst_mem_wb_inter (); interface VX_inst_mem_wb_if ();
wire [`NUM_THREADS-1:0][31:0] loaded_data; wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc; wire [31:0] mem_wb_pc;

2
hw/rtl/interfaces/VX_inst_meta_inter.v → hw/rtl/interfaces/VX_inst_meta_if.v
View File

@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_inst_meta_inter (); interface VX_inst_meta_if ();
wire [31:0] instruction; wire [31:0] instruction;
wire [31:0] inst_pc; wire [31:0] inst_pc;

2
hw/rtl/interfaces/VX_jal_response_inter.v → hw/rtl/interfaces/VX_jal_response_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_jal_response_inter (); interface VX_jal_response_if ();
wire jal; wire jal;
wire [31:0] jal_dest; wire [31:0] jal_dest;

2
hw/rtl/interfaces/VX_join_inter.v → hw/rtl/interfaces/VX_join_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_join_inter (); interface VX_join_if ();
wire is_join; wire is_join;
wire [`NW_BITS-1:0] join_warp_num; wire [`NW_BITS-1:0] join_warp_num;

2
hw/rtl/interfaces/VX_lsu_req_inter.v → hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_lsu_req_inter (); interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid; wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc; wire [31:0] lsu_pc;

2
hw/rtl/interfaces/VX_mem_req_inter.v → hw/rtl/interfaces/VX_mem_req_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_mem_req_inter (); interface VX_mem_req_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [2:0] mem_read; wire [2:0] mem_read;

2
hw/rtl/interfaces/VX_mw_wb_inter.v → hw/rtl/interfaces/VX_mw_wb_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_mw_wb_inter (); interface VX_mw_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] mem_result; wire [`NUM_THREADS-1:0][31:0] mem_result;

2
hw/rtl/interfaces/VX_warp_ctl_inter.v → hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -4,7 +4,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_warp_ctl_inter (); interface VX_warp_ctl_if ();
wire [`NW_BITS-1:0] warp_num; wire [`NW_BITS-1:0] warp_num;
wire change_mask; wire change_mask;

2
hw/rtl/interfaces/VX_wb_inter.v → hw/rtl/interfaces/VX_wb_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_wb_inter (); interface VX_wb_if ();
wire [`NUM_THREADS-1:0][31:0] write_data; wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc; wire [31:0] wb_pc;

2
hw/rtl/interfaces/VX_wstall_inter.v → hw/rtl/interfaces/VX_wstall_if.v
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@@ -3,7 +3,7 @@
`include "../VX_define.vh" `include "../VX_define.vh"
interface VX_wstall_inter(); interface VX_wstall_if();
wire wstall; wire wstall;
wire [`NW_BITS-1:0] warp_num; wire [`NW_BITS-1:0] warp_num;

4
hw/rtl/pipe_regs/VX_d_e_reg.v
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@@ -5,8 +5,8 @@ module VX_d_e_reg (
input wire reset, input wire reset,
input wire in_branch_stall, input wire in_branch_stall,
input wire in_freeze, input wire in_freeze,
VX_frE_to_bckE_req_inter vx_frE_to_bckE_req, VX_frE_to_bckE_req_if vx_frE_to_bckE_req,
VX_frE_to_bckE_req_inter vx_bckE_req VX_frE_to_bckE_req_if vx_bckE_req
); );
wire stall = in_freeze; wire stall = in_freeze;

4
hw/rtl/pipe_regs/VX_f_d_reg.v
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@@ -5,8 +5,8 @@ module VX_f_d_reg (
input wire reset, input wire reset,
input wire in_freeze, input wire in_freeze,
VX_inst_meta_inter fe_inst_meta_fd, VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de VX_inst_meta_if fd_inst_meta_de
); );

4
hw/rtl/pipe_regs/VX_i_d_reg.v
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@@ -5,8 +5,8 @@ module VX_i_d_reg (
input wire reset, input wire reset,
input wire in_freeze, input wire in_freeze,
VX_inst_meta_inter fe_inst_meta_fd, VX_inst_meta_if fe_inst_meta_fd,
VX_inst_meta_inter fd_inst_meta_de VX_inst_meta_if fd_inst_meta_de
); );

4
hw/rtl/shared_memory/VX_shared_memory_block.v
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@@ -61,7 +61,7 @@ module VX_shared_memory_block
end end
// Using ASIC MEM // Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */ `IGNORE_WARNINGS_BEGIN
rf2_128x128_wm1 first_ram ( rf2_128x128_wm1 first_ram (
.CENYA(), .CENYA(),
.AYA(), .AYA(),
@@ -98,7 +98,7 @@ module VX_shared_memory_block
.SEB(1'b0), .SEB(1'b0),
.COLLDISN(1'b1) .COLLDISN(1'b1)
); );
/* verilator lint_on PINCONNECTEMPTY */ `IGNORE_WARNINGS_END
`endif `endif

12
simX/cache_simX.v
View File

@@ -25,7 +25,7 @@ module cache_simX (
//////////////////// ICACHE /////////////////// //////////////////// ICACHE ///////////////////
VX_icache_request_inter VX_icache_req; VX_icache_request_if VX_icache_req;
assign VX_icache_req.pc_address = in_icache_pc_addr; assign VX_icache_req.pc_address = in_icache_pc_addr;
assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ; assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE; assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
@@ -33,11 +33,11 @@ module cache_simX (
assign VX_icache_req.out_cache_driver_in_data = 0; assign VX_icache_req.out_cache_driver_in_data = 0;
VX_icache_response_inter VX_icache_rsp; VX_icache_response_if VX_icache_rsp;
assign out_icache_stall = VX_icache_rsp.delay; assign out_icache_stall = VX_icache_rsp.delay;
VX_dram_req_rsp_inter #( VX_dram_req_rsp_if #(
.NUMBER_BANKS(`ICACHE_BANKS), .NUMBER_BANKS(`ICACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK) .NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)
@@ -52,7 +52,7 @@ module cache_simX (
//////////////////// DCACHE /////////////////// //////////////////// DCACHE ///////////////////
VX_dcache_request_inter VX_dcache_req; VX_dcache_request_if VX_dcache_req;
assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read; assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write; assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write;
assign VX_dcache_req.out_cache_driver_in_data = 0; assign VX_dcache_req.out_cache_driver_in_data = 0;
@@ -64,11 +64,11 @@ module cache_simX (
assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t]; assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t];
end end
VX_dcache_response_inter VX_dcache_rsp; VX_dcache_response_if VX_dcache_rsp;
assign out_dcache_stall = VX_dcache_rsp.delay; assign out_dcache_stall = VX_dcache_rsp.delay;
VX_dram_req_rsp_inter #( VX_dram_req_rsp_if #(
.NUMBER_BANKS(`DCACHE_BANKS), .NUMBER_BANKS(`DCACHE_BANKS),
.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK) .NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)