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Synthesis Compatible

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This commit is contained in:
Lyons, Ethan Tyler
2019-11-21 21:41:41 -05:00
committed by GitHub Enterprise
parent e56e42c8c3
commit b748a7665d
1 changed files with 7 additions and 1 deletions
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8
rtl/cache/VX_d_cache.v vendored
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@@ -304,9 +304,15 @@ module VX_d_cache
// 0;
wire[1:0] byte_select = bank_addr[1:0];
wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START];
`ifdef SYN_FUNC
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = 0;
wire[IND_SIZE_END:IND_SIZE_START] cache_index = 0;
`else
wire[OFFSET_SIZE_END:OFFSET_SIZE_START] cache_offset = bank_addr[ADDR_OFFSET_END:ADDR_OFFSET_START];
wire[IND_SIZE_END:IND_SIZE_START] cache_index = bank_addr[ADDR_IND_END:ADDR_IND_START];
wire[TAG_SIZE_END:TAG_SIZE_START] cache_tag = bank_addr[ADDR_TAG_END:ADDR_TAG_START];
`endif
wire normal_valid_in = valid_per_bank[bank_id];