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Fixing a bug in a fix...

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felsabbagh3
2020-03-29 13:52:22 -07:00
parent cd418a1f96
commit eb6e0cee43
1 changed files with 1 additions and 1 deletions
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2
rtl/VX_cache/VX_cache_miss_resrv.v
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@@ -96,7 +96,7 @@ module VX_cache_miss_resrv
// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE );
assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size == (MRVQ_SIZE-4));
assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5));
wire enqueue_possible = !miss_resrv_full;
wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;