felsabbagh3
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5b633bca61
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FIX
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2020-04-05 00:17:02 -07:00 |
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felsabbagh3
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91a926e3b6
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-04 22:59:17 -07:00 |
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felsabbagh3
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913670a7bb
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Fixed Dependancy List in VX_alu that doesn't update when multiply is ready
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2020-04-04 22:56:31 -07:00 |
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Blaise Tine
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18f1350fdf
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update
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2020-04-05 01:38:11 -04:00 |
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Blaise Tine
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256dec4768
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changing demo to use addition
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2020-04-05 01:32:57 -04:00 |
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felsabbagh3
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9b989cec69
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Fixed use before init
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2020-04-04 18:41:25 -07:00 |
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felsabbagh3
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165836332c
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Fixed snp delay for sm
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2020-04-04 18:21:25 -07:00 |
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felsabbagh3
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bcea9866a7
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Fixed a couple of things
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2020-04-04 18:20:06 -07:00 |
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felsabbagh3
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d0765b8fb1
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Now Flush Routine only sends one round of snoops
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2020-04-04 18:02:57 -07:00 |
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felsabbagh3
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65fa9285bf
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Fixed Flushing and Prefetching
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2020-04-04 17:57:35 -07:00 |
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felsabbagh3
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a7a1906bea
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-04 10:14:24 -07:00 |
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felsabbagh3
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70bd673031
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Resseting GPR
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2020-04-04 10:13:26 -07:00 |
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Blaise Tine
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0a8d829f15
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basic test update
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2020-04-04 09:07:04 -04:00 |
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Blaise Tine
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07ec0ef344
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OPAE hw snooping fixes
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2020-04-04 05:07:45 -07:00 |
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Blaise Tine
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1f63139ce5
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fix RTL code undefined variables
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2020-04-03 22:59:40 -07:00 |
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Blaise Tine
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41f3245376
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enable Vortex compiler to support using environment path
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2020-04-03 20:24:57 -04:00 |
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Blaise Tine
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5e54bdffe9
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POCL compiler with relative path
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2020-04-03 17:47:55 -04:00 |
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codetector
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621e0b2a25
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-04-03 15:06:58 -04:00 |
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Blaise Tine
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6ae9a6732b
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-03 15:04:15 -04:00 |
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codetector
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9ee12d4a01
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-04-03 14:36:52 -04:00 |
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felsabbagh3
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10e445d459
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Provisioned Prefetching, currently disabled
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2020-04-03 00:30:33 -07:00 |
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Blaise Tine
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c05ea79afa
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-03 00:13:46 -04:00 |
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Blaise Tine
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66a879608e
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udpated OpenCL runtime to include cache flushing
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2020-04-03 00:13:24 -04:00 |
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felsabbagh3
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8ad75e0442
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-02 20:26:46 -07:00 |
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felsabbagh3
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7d1cc5234e
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Fixed dram_fill_accept dependant on input address
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2020-04-02 20:26:37 -07:00 |
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Blaise Tine
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ee77c76785
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-02 20:09:20 -07:00 |
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Blaise Tine
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f590d6acc8
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minor update
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2020-04-02 20:09:08 -07:00 |
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felsabbagh3
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8c1b72691f
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Updated head location to 9-a
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2020-04-02 19:41:53 -07:00 |
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Blaise Tine
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fbda21d5f5
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-02 19:38:49 -07:00 |
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felsabbagh3
|
478c3cf21d
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-02 19:19:31 -07:00 |
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felsabbagh3
|
0e0b326b31
|
Removed bank Hazard Signals
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2020-04-02 19:19:00 -07:00 |
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Blaise Tine
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5b9ee0bb7b
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-02 16:01:52 -07:00 |
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Blaise Tine
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bc6b2969ef
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minor opae hw fixed
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2020-04-02 15:41:12 -07:00 |
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codetector
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26b9fef2d8
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remove binaries
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2020-04-02 14:20:14 -04:00 |
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codetector
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00f202bddb
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two more benchmarks
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2020-04-02 14:16:16 -04:00 |
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codetector
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c6319a0dbd
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more gitignore update
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2020-04-02 14:16:02 -04:00 |
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codetector
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b9e5612949
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fix gitignore
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2020-04-02 14:13:48 -04:00 |
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codetector
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abc0624086
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fix makefile
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2020-04-02 14:13:38 -04:00 |
|
codetector
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299e3aa72f
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kmeans should compile with new loading methid
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2020-04-02 14:08:57 -04:00 |
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Blaise Tine
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6463cca529
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extending basic test
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2020-04-02 08:46:32 -07:00 |
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Blaise Tine
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efd3c1d154
|
udpate
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2020-04-02 06:51:11 -04:00 |
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Blaise Tine
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f7b7c509d5
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udpate
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2020-04-02 05:16:13 -04:00 |
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Blaise Tine
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7e4399e3ac
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OPAE HW full redesign - basic test passing
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2020-04-02 05:10:51 -04:00 |
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felsabbagh3
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7b4b44e5ab
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Fixed DRAM random latency simulator
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2020-03-31 20:33:45 -07:00 |
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felsabbagh3
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1b9d9f3625
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Fixed incorrect miss_add on pipeline stall
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2020-03-31 20:23:09 -07:00 |
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Blaise Tine
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bca5ac5e7f
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enable rtl sim dram stalls
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2020-03-31 02:41:14 -04:00 |
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Blaise Tine
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e92c4b6774
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enable rtl sim dram stalls
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2020-03-31 02:38:18 -04:00 |
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felsabbagh3
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ba8bc95c90
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Newlib update
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2020-03-30 23:08:38 -07:00 |
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felsabbagh3
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bcf894b581
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Demo SOC W=8, T=4 Passing
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2020-03-30 22:17:38 -07:00 |
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felsabbagh3
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66a837b0df
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SOC only 2 errors
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2020-03-30 21:28:40 -07:00 |
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