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9110e8367e18496c090a8d0c1a3e157e435c8caf
kernels/rtl
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Elsabbagh 9110e8367e modelsim
2019-10-25 23:41:34 -04:00
..
cache
NUM_REQ
2019-10-25 13:46:31 -04:00
icarus
Trying icarus
2019-10-25 22:54:02 -04:00
interfaces
FIxed first circular issue
2019-10-24 10:38:04 -04:00
modelsim
modelsim
2019-10-25 23:41:34 -04:00
pipe_regs
Added ISA2 infrastructure with bugs
2019-10-18 05:21:32 -04:00
quartus
Full Evaluation Attempt 1
2019-09-11 01:39:00 -04:00
shared_memory
Fixed SM + added def SYN
2019-10-22 15:56:30 -04:00
simulate
Parametized cache
2019-10-25 13:36:06 -04:00
.DS_Store
New RF with Evaluation
2019-09-11 01:04:23 -04:00
byte_enabled_simple_dual_port_ram.v
Need to link SystemC for sc_time_stamp()
2019-10-14 23:25:14 -04:00
Makefile
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
results.txt
CACHE FINALLY WORKING
2019-10-25 04:01:23 -04:00
Vortex.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
VX_alu.v
Added CSR TID/WID reads
2019-10-21 02:10:05 -04:00
VX_back_end.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
VX_csr_handler.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_csr_wrapper.v
Added CSR TID/WID reads
2019-10-21 02:10:05 -04:00
VX_decode.v
WSPAWN imp + tested
2019-10-21 23:35:53 -04:00
VX_define.v
Parametized cache
2019-10-25 13:36:06 -04:00
VX_dmem_controller.v
NUM_REQ
2019-10-25 13:46:31 -04:00
VX_execute_unit.v
Cleanup before integration
2019-10-22 03:03:17 -04:00
VX_fetch.v
Barriers impl + tested
2019-10-22 01:47:39 -04:00
VX_front_end.v
FIxed first circular issue
2019-10-24 10:38:04 -04:00
VX_generic_priority_encoder.v
Finished cache not tested
2019-10-23 19:07:26 -04:00
VX_generic_register.v
reset posedge
2019-10-21 11:34:12 -04:00
VX_generic_stack.v
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
VX_gpgpu_inst.v
Cleanup before integration
2019-10-22 03:03:17 -04:00
VX_gpr_stage.v
Fixed SM + added def SYN
2019-10-22 15:56:30 -04:00
VX_gpr_wrapper.v
Cleanup
2019-10-18 02:20:38 -04:00
VX_gpr.v
Fixed SM + added def SYN
2019-10-22 15:56:30 -04:00
VX_inst_multiplex.v
Added CSR TID/WID reads
2019-10-21 02:10:05 -04:00
VX_lsu_addr_gen.v
Instruction Multiplex LSU/EXU 1 cycle DONE
2019-10-17 22:29:21 -04:00
VX_lsu.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
VX_one_counter.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_priority_encoder_w_mask.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
VX_priority_encoder.v
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
VX_rename.v
Moved GPR to back-end
2019-10-14 19:08:32 -04:00
VX_scheduler.v
Cleanup before integration
2019-10-22 03:03:17 -04:00
VX_warp_scheduler.v
Cleanup before integration
2019-10-22 03:03:17 -04:00
VX_warp.v
Full Evaluation Attempt 1
2019-09-11 01:39:00 -04:00
VX_writeback.v
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00