Hansung Kim
d0ba68852e
Relax timeout for stale srcId in NewSourceGenerator
2024-03-07 15:58:24 -08:00
Hansung Kim
56ef9012ee
Streamline perf counter code
2024-03-07 15:02:43 -08:00
Hansung Kim
34de55ee13
Fix missing Vortex modules for upstream merge; add perf modules
2024-03-07 15:01:39 -08:00
Hansung Kim
7aacd21b42
Bump vortex with upstream merge
2024-03-07 15:01:15 -08:00
Hansung Kim
0fa2712897
Add perf counters for smem/dmem latency
2024-03-04 21:10:19 -08:00
Hansung Kim
b3a9207136
Tie tile smem ports together using Xbars; comment-out Gemmini spad
...
TODO pull Gemmini out to the cluster as well
2024-03-04 13:45:54 -08:00
Hansung Kim
805651a11b
Add RadianceCluster
2024-03-02 15:46:11 -08:00
Hansung Kim
339f559b43
Update NUM_THREADS/WARPS in accordance to RadianceConfig
2024-02-29 17:53:19 -08:00
Hansung Kim
c05897abfc
Add rocket-chip cluster support in WithRadianceCores
2024-02-29 17:37:54 -08:00
Hansung Kim
55d00d25bb
Parametrize numWarps / numCoreLanes / numMemLanes
2024-02-27 18:55:02 -08:00
Richard Yan
ae6e739655
fix gemmini config specification and add buffer
2024-02-24 00:33:41 -08:00
Richard Yan
7f78f6bd2f
bug fixes for address rewriter
2024-02-07 14:45:55 -08:00
Hansung Kim
9451f513bf
Explicitly disable LSU dedup in Vortex core
...
Our coalescer handles this on its own, and this makes trace verification
easier (so that all-same-address reqs still show up as tmask 1111.)
2024-02-06 22:34:29 -08:00
Hansung Kim
0384324e83
Fix wrong width for lookup srcId in InFlightTable
2024-02-06 22:33:51 -08:00
Richard Yan
7cfa994890
bug fix for address rewriter
2024-02-05 12:01:49 -08:00
Hansung Kim
da8256fdb8
Doc update
2024-02-05 09:45:13 -08:00
Hansung Kim
89c902c44f
Bump vortex to upstream; fix addResource path accordingly
2024-02-05 09:45:13 -08:00
Hansung Kim
064f4f8541
Move EXTRA_SIM_PREPROC_DEFINES to mk fragment
2024-02-05 09:45:13 -08:00
Hansung Kim
6d2f89c6ae
Remaining renames
2024-02-05 09:44:55 -08:00
Hansung Kim
3224019114
Rename VortexTile -> RadianceTile
2024-02-05 09:43:30 -08:00
Richard Yan
9b0aa387c3
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-02-02 15:55:17 -08:00
Richard Yan
f3cee5abff
enable gpu to use separate physical memory range
2024-02-02 15:55:02 -08:00
Hansung Kim
2fcb1f374f
Rename to RadianceTile.scala
2024-02-01 14:42:43 -08:00
Richard Yan
20191a9253
Merge branch 'main' of https://github.com/hansungk/radiance into main
2024-01-31 13:13:55 -08:00
Richard Yan
e20799a7e1
make shared memory use external spad
2024-01-31 13:13:06 -08:00
Hansung Kim
2aab555f0a
Connect unified_mem_node from Gemmini
2024-01-30 18:01:32 -08:00
Hansung Kim
a648b388ef
Bump radpie
2024-01-30 18:01:19 -08:00
Hansung Kim
dc86d69da4
Add make fragment
2024-01-29 15:40:15 -08:00
Hansung Kim
2c7d8650d4
Bump radpie
2024-01-29 13:58:34 -08:00
Hansung Kim
149f8b193e
Add memfuzzer DPI library as submodule
2024-01-29 13:18:58 -08:00
Hansung Kim
16c4292e57
Rename core.io.cease to finished; bump vortex
2024-01-26 14:25:12 -08:00
Hansung Kim
cfce029b70
Generate explicit clock domain in CanHaveMemtraceCore
2024-01-26 00:13:14 -08:00
Hansung Kim
78075e5148
Bump vortex
2024-01-25 23:24:05 -08:00
Hansung Kim
df26764fc0
Reduce sharedmem addr mapping to 8KB
...
smem size is set to 16KB, and reqs exceeding this range gets filtered
out of smemNodes from inside the core. Lower 8KB is mapped to smem
banks, and upper 8KB is reserved for MMIO.
2024-01-23 22:15:40 -08:00
Hansung Kim
17553ccfcd
Connect stlNode of Gemmini
2024-01-23 18:58:03 -08:00
Hansung Kim
2e5f6d8427
Support RoCC instantiation in VortexTile
2024-01-23 16:24:55 -08:00
Hansung Kim
d2032b563c
Don't set XLen in WithRadianceCores
...
Currently Vortex core uses hardcoded 32-bit xlen in its RTL. Also, setting this
here breaks instantiating Gemmini, which assumes 64bit. So just leave it
unchanged and try to treat Vortex as a special-case.
2024-01-23 16:11:32 -08:00
Hansung Kim
34fce0e34d
Commented out TLRAMCoalescerFuzzer test module
2024-01-23 13:47:22 -08:00
Hansung Kim
164e722790
Pass inflight to DPI to determine proper fuzz termination
2024-01-23 01:11:52 -08:00
Hansung Kim
f26c9dfb11
Put pipereg between uncoalescer output and respQueue
...
... to break the combinational loop resulting from MultiPortQueue's
enq.ready port being dependent on enq.valid. This seems to manifest
only when time-coalescing is enabled.
2024-01-22 17:34:34 -08:00
Hansung Kim
75d51e3d1d
Distinguish time-coalescing window from request queue depth
2024-01-22 14:39:34 -08:00
Hansung Kim
b2a83c788e
Pass both A and D bundles to memfuzzer DPI
2024-01-22 01:54:45 -08:00
Hansung Kim
e7340ba840
Use negedge for DPI calls to avoid confusion
2024-01-22 01:51:35 -08:00
Hansung Kim
a499dfff32
Enable conditional instantiation of coalescer in FuzzerTile
2024-01-22 01:43:09 -08:00
Hansung Kim
80414964f0
Remove unnecessary id.bits from SourceGenerator table row
2024-01-22 01:41:24 -08:00
Hansung Kim
ec02a12220
Use DecoupledIO instead of explicit valid in TraceLine bundle
2024-01-21 17:50:00 -08:00
Hansung Kim
d56981a0b1
Fix io.finished of MemTraceDriver not waiting for inflight responses
2024-01-21 15:33:15 -08:00
Hansung Kim
e183606193
Write basic DPI mem fuzzer
2024-01-20 21:47:06 -08:00
Hansung Kim
6ff127eb51
Write faux memory fuzzer
2024-01-19 22:37:44 -08:00
Hansung Kim
9e7a8f4ef2
Add FuzzerTile
...
This tile is similar to TraceGenTile in rocket-chip, where each tile
contains a memtrace generator/fuzzer that drives the intra-tile
coalescer and the rest of the memory subsystem.
2024-01-19 22:05:21 -08:00
