Richard Yan
6488cb5c78
support no gemminis, trim debug prints
2024-11-11 16:14:02 -08:00
Hansung Kim
465322af38
Merge branch 'new-cisc'
2024-11-09 22:36:27 -08:00
Hansung Kim
8056fa4ada
Bump vortex
2024-11-09 22:35:40 -08:00
Hansung Kim
31f0905567
Add new opcode for compute and spad mvout
2024-11-09 22:35:14 -08:00
Hansung Kim
ca63c9fa74
Bump vortex
2024-11-08 21:53:21 -08:00
Richard Yan
c87858b6f4
new cisc operations
2024-11-08 20:49:49 -08:00
Richard Yan
0c6618c65d
back to non-blocking read
2024-11-07 18:20:37 -08:00
Richard Yan
d49abf97ff
amend config based on gemmini update
2024-11-03 21:07:06 -08:00
Richard Yan
9a5af03672
blocking gemmini fence and bump vortex
2024-11-01 02:45:08 -07:00
Hansung Kim
99da429cb1
tensor: Move C reg access to execute stage for higher util
...
This prevents coupling between C access in frontend & queue freeup in
backend.
2024-10-29 17:51:32 -07:00
Hansung Kim
37b8b6470b
Bump vortex with race fix
2024-10-29 14:50:26 -07:00
Hansung Kim
216cfb0589
Bump vortex
2024-10-28 23:39:58 -07:00
Hansung Kim
752effdb21
tensor: Add FIFOFixer to smem tensor port
...
TODO: get area result for this
2024-10-28 23:38:56 -07:00
Hansung Kim
daabeb03ab
tensor: Fix wrong addressGen that used bits not bytes
2024-10-28 22:27:34 -07:00
Hansung Kim
1ae1965580
tensor: Add IO and latching for smem address
2024-10-28 19:28:45 -07:00
Hansung Kim
c22fd20616
Bump vortex to 8cores
2024-10-27 19:47:52 -07:00
Hansung Kim
0e389dc362
Bump vortex
2024-10-27 18:49:42 -07:00
Hansung Kim
0ba61aabb6
tensor: Instantiate correct fake tcore module according to parameter
...
This has to align with what the verilog source actually uses.
2024-10-27 18:48:44 -07:00
Hansung Kim
13b9577723
Instantiate fake tensor modules outside of diplomacy
...
Adding them to the Diplomacy graph will cause to widen source widths
which can have area implications.
This gets rid of the need to do addResource() calls to the manually
generated Verilog files. Their module parameters should be kept the
same as what's used in the parent Verilog module, however.
2024-10-25 23:02:25 -07:00
Hansung Kim
543eb2feb4
tensor: Support FP16 in TensorCoreDecoupled
2024-10-25 22:26:04 -07:00
Hansung Kim
eed821eda6
tensor: Add test for 8-dim fp16 DPU
2024-10-25 21:57:28 -07:00
Hansung Kim
46a57fdf9b
tensor: Parameterize dimension in TensorDotProductUnit
2024-10-25 21:57:22 -07:00
Hansung Kim
51dfebb6a7
tensor: Support pipe = 1 in FillBuffer for higher throughput
2024-10-25 20:20:53 -07:00
Hansung Kim
d46a343239
tensor: Fix metadata of C req; fix dequeue / req gen timing
2024-10-25 19:13:42 -07:00
Hansung Kim
1a1a4a088d
tensor: Fix access state transition to consider C req
2024-10-25 18:23:51 -07:00
Hansung Kim
991025e896
tensor: Fix C reg being dropped by checking space in respQueueC
2024-10-25 18:10:35 -07:00
Hansung Kim
81efecb3c8
tensor: Fix timing of fullCTag
2024-10-25 17:29:35 -07:00
Hansung Kim
43e064fe82
tensor: Add access logic for C from regfile
2024-10-25 15:22:52 -07:00
Hansung Kim
fc5b864b86
Bump vortex; addResource tensor regfile if
2024-10-24 20:35:14 -07:00
Hansung Kim
31fa440000
Bump vortex
2024-10-24 15:25:12 -07:00
Hansung Kim
ccfb467587
Bump vortex
2024-10-24 15:24:28 -07:00
Hansung Kim
988f0e3174
smem: Disable sanity check on partialData
2024-10-24 15:24:28 -07:00
Hansung Kim
f989bfccc2
Add tensorCoreDecoupled param to WithRadianceCores
2024-10-24 15:24:28 -07:00
Richard Yan
68e715e284
fix unaligned port
2024-10-24 13:42:45 -07:00
Richard Yan
9b8d16d184
Merge branch 'main' of https://github.com/ucb-bar/radiance into main
2024-10-23 15:09:48 -07:00
Richard Yan
0a54018650
dual read port srams
2024-10-23 15:09:43 -07:00
Hansung Kim
2a8c488d28
tensor: Reassert initiate.ready as soon as access ready
2024-10-22 23:10:11 -07:00
Hansung Kim
95ecc5180f
tensor: Decouple warp in execute from access
...
This allows the access stage to accept new initiate back-to-back without
waiting for the previous writeback to finish.
2024-10-22 22:44:33 -07:00
Hansung Kim
072904a82b
Bump vortex
2024-10-22 22:06:24 -07:00
Hansung Kim
0a682fb6ef
tensor: dontTouch TensorDPU io
...
Prevents bits.c from being optimized out and set to Z in
TensorCoreDecoupled.
2024-10-22 17:55:14 -07:00
Hansung Kim
85eb5e334f
Bump vortex
2024-10-22 17:47:54 -07:00
Hansung Kim
b566748bcb
tensor: Address gen for block-wise contiguous layout
...
Necessary to meet 32B-alignment requirement for SMEM.
2024-10-22 17:17:08 -07:00
Hansung Kim
54ce0f7c34
tensor: Increase numSourceId to 16 to match RadianceTile
2024-10-22 17:08:38 -07:00
Hansung Kim
8818fc9203
tensor: Fix tagWidth for tensor mem io
2024-10-22 16:29:33 -07:00
Hansung Kim
c613341a77
Disable addPath for old verilog; Deassert valid for tensor core
...
There's an uncaught TL source bug when the core is busy, which doesn't
really need to be fixed with this.
2024-10-22 15:02:55 -07:00
Hansung Kim
83c1e9a0be
Merge branch 'tensor-decoupled'
2024-10-22 14:35:44 -07:00
Hansung Kim
e705e8557f
Fake tensor core at RadianceTile for Verilog unique-ification
2024-10-22 14:33:10 -07:00
Hansung Kim
d705843c9c
Merge commit 'origin/main~1'
2024-10-21 22:41:03 -07:00
Hansung Kim
0fe2b3b07e
Bump vortex
2024-10-21 22:39:28 -07:00
Hansung Kim
408888ae8f
tensor: addPath()s for hopper generated chisel
...
FIXME: SourceGenerator has a name-clash.
2024-10-21 22:38:53 -07:00
