wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

RTL code refactoring

Browse Source
This commit is contained in:
Blaise Tine
2020-04-20 13:52:24 -04:00
parent 94e4f056db
commit 1a2823da0d
31 changed files with 253 additions and 260 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
hw/rtl/cache/VX_bank.v vendored
View File

@@ -125,9 +125,9 @@ module VX_bank #(
.clk (clk),
.reset (reset),
.push (snp_req_valid),
.in_data (snp_req_addr),
.data_i (snp_req_addr),
.pop (snrq_pop),
.out_data(snrq_addr_st0),
.data_o (snrq_addr_st0),
.empty (snrq_empty),
.full (snp_req_full)
);
@@ -147,9 +147,9 @@ module VX_bank #(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp_valid),
.in_data ({dram_fill_rsp_addr, dram_fill_rsp_data}),
.data_i ({dram_fill_rsp_addr, dram_fill_rsp_data}),
.pop (dfpq_pop),
.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
.data_o({dfpq_addr_st0, dfpq_filldata_st0}),
.empty (dfpq_empty),
.full (dfpq_full)
);
@@ -538,10 +538,10 @@ module VX_bank #(
.reset (reset),
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.data_i ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.pop (core_rsp_pop),
.out_data({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}),
.data_o({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}),
.empty (cwbq_empty),
.full (cwbq_full)
);
@@ -606,10 +606,10 @@ module VX_bank #(
.reset (reset),
.push (dwbq_push),
.in_data ({dwbq_req_addr, dwbq_req_data}),
.data_i ({dwbq_req_addr, dwbq_req_data}),
.pop (dram_wb_req_pop),
.out_data({dram_wb_req_addr, dram_wb_req_data}),
.data_o({dram_wb_req_addr, dram_wb_req_data}),
.empty (dwbq_empty),
.full (dwbq_full)
);
@@ -627,9 +627,9 @@ module VX_bank #(
.clk (clk),
.reset (reset),
.push (snp_fwd_push),
.in_data ({addr_st2}),
.data_i ({addr_st2}),
.pop (snp_fwd_pop),
.out_data({snp_fwd_addr}),
.data_o({snp_fwd_addr}),
.empty (ffsq_empty),
.full (ffsq_full)
);

4
hw/rtl/cache/VX_cache_dfq_queue.v vendored
View File

@@ -79,9 +79,9 @@ module VX_cache_dfq_queue #(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
.data_i ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
.pop (pop_qual),
.out_data({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
.data_o({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
.empty (o_empty),
.full (dfqq_full)
);

4
hw/rtl/cache/VX_cache_req_queue.v vendored
View File

@@ -122,9 +122,9 @@ module VX_cache_req_queue #(
.clk (clk),
.reset (reset),
.push (push_qual),
.in_data ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}),
.data_i ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}),
.pop (pop_qual),
.out_data ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}),
.data_o ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}),
.empty (o_empty),
.full (reqq_full)
);

4
hw/rtl/cache/VX_prefetcher.v vendored
View File

@@ -40,10 +40,10 @@ module VX_prefetcher #(
.reset (reset),
.push (dram_req && !current_full && !pref_pop),
.in_data (dram_req_addr & `BASE_ADDR_MASK),
.data_i (dram_req_addr & `BASE_ADDR_MASK),
.pop (update_use),
.out_data(current_addr),
.data_o(current_addr),
.empty (current_empty),
.full (current_full)