tensor: Decode rs1/rs2 of HGMMA for smem addresses

hw/rtl/core/VX_decode.sv

@@ -551,15 +551,16 @@ module VX_decode  #(
                 end else begin
                     op_type = `INST_TENSOR_HGMMA;
                 end
-                // rd/rs1/rs2/rs3 unused to prevent hazard stalls at the
-                // scoreboard
+                // rs1 and rs2 encodes the sharedmem addresses for A and
+                // B matrix tiles
+                `USED_IREG (rs1);
+                `USED_IREG (rs2);
             `else
                 ex_type = `EX_TENSOR;
                 op_type = `INST_TENSOR_HMMA;
                 // tensor core macroop is encoded as r-type
                 // hazard stall logic in the scoreboard will handle
                 // read-after-write dependency on rd -> rs3
-                use_rd = 1;
                 `USED_IREG (rd);
                 `USED_IREG (rs1);
                 `USED_IREG (rs2);