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tensor: Decode rs1/rs2 of HGMMA for smem addresses

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Hansung Kim
2024-10-28 19:41:37 -07:00
parent 72db04cec0
commit 4376bd33a2
1 changed files with 4 additions and 3 deletions
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7
hw/rtl/core/VX_decode.sv
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@@ -551,15 +551,16 @@ module VX_decode #(
end else begin end else begin
op_type = `INST_TENSOR_HGMMA; op_type = `INST_TENSOR_HGMMA;
end end
// rd/rs1/rs2/rs3 unused to prevent hazard stalls at the // rs1 and rs2 encodes the sharedmem addresses for A and
// scoreboard // B matrix tiles
`USED_IREG (rs1);
`USED_IREG (rs2);
`else `else
ex_type = `EX_TENSOR; ex_type = `EX_TENSOR;
op_type = `INST_TENSOR_HMMA; op_type = `INST_TENSOR_HMMA;
// tensor core macroop is encoded as r-type // tensor core macroop is encoded as r-type
// hazard stall logic in the scoreboard will handle // hazard stall logic in the scoreboard will handle
// read-after-write dependency on rd -> rs3 // read-after-write dependency on rd -> rs3
use_rd = 1;
`USED_IREG (rd); `USED_IREG (rd);
`USED_IREG (rs1); `USED_IREG (rs1);
`USED_IREG (rs2); `USED_IREG (rs2);