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scope refactoring

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This commit is contained in:
Blaise Tine
2020-10-03 18:53:21 -04:00
parent 878c89861b
commit 4e1007e5b2
28 changed files with 1014 additions and 693 deletions
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11
driver/opae/Makefile
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@@ -1,11 +1,14 @@
OPAE_HOME ?= /tools/opae/1.4.0
#CXXFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors
CXXFLAGS += -I../include -I$(OPAE_HOME)/include -I../../hw
LDFLAGS += -L$(OPAE_HOME)/lib
SCOPE=1
# stack execution protection
LDFLAGS +=-z noexecstack
@@ -22,7 +25,11 @@ CXXFLAGS += -fPIC
CXXFLAGS += -DDUMP_PERF_STATS
# Enable scope analyzer
#CXXFLAGS += -DSCOPE
# Enable scope analyzer
ifdef SCOPE
CXXFLAGS += -DSCOPE
SET_SCOPE = SCOPE=1
endif
LDFLAGS += -shared
@@ -64,7 +71,7 @@ vlsim: $(SRCS) opae-vlsim
$(CXX) $(CXXFLAGS) -L./vlsim -DUSE_VLSIM $(SRCS) $(LDFLAGS) $(VLSIM_LIBS) -o $(PROJECT_VLSIM)
opae-vlsim:
$(MAKE) -C vlsim
$(SET_SCOPE) $(MAKE) -C vlsim
vortex.o: vortex.cpp
$(CXX) $(CXXFLAGS) -c vortex.cpp -o $@

24
driver/opae/vlsim/Makefile
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@@ -12,6 +12,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
@@ -21,7 +23,8 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#DEBUG=1
DEBUG=1
#SCOPE=1
CFLAGS += -fPIC
@@ -34,7 +37,7 @@ LDFLAGS += -shared -pthread
TOP = vortex_afu_shim
RTL_DIR = ../../../hw/rtl
RTL_DIR=../../../hw/rtl
SRCS = fpga.cpp opae_sim.cpp
SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
@@ -60,20 +63,27 @@ else
CFLAGS += -DNDEBUG
endif
# Enable scope analyzer
ifdef SCOPE
VL_FLAGS += -DSCOPE
CFLAGS += -DSCOPE
SCOPE_CFG = scope
endif
VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
# Enable scope analyzer
#VL_FLAGS += -DSCOPE
#CFLAGS += -DSCOPE
RTL_INCLUDE += -I../../../hw/opae -I../../../hw/opae/ccip
PROJECT = libopae-c-vlsim.so
all: $(PROJECT)
$(PROJECT): $(SRCS)
# generate scope data
scope: ../../../hw/scripts/scope.json
../../../hw/scripts/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl ../../../hw/rtl/scope-defs.vh ../../../hw/scripts/scope.json
$(PROJECT): $(SRCS) $(SCOPE_CFG)
verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk

4
driver/opae/vlsim/opae_sim.cpp
View File

@@ -135,6 +135,10 @@ void opae_sim::step() {
this->sRxPort_bus();
this->sTxPort_bus();
this->avs_bus();
#ifndef NDEBUG
fflush(stdout);
#endif
}
void opae_sim::eval() {

4
driver/opae/vortex.cpp
View File

@@ -509,11 +509,11 @@ extern int vx_start(vx_device_h hdevice) {
// start execution
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN));
#ifdef SCOPE
/*#ifdef SCOPE
sleep(15);
vx_scope_stop(device->fpga, 0);
exit(0);
#endif
#endif*/
return 0;
}

137
driver/opae/vx_scope.cpp
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@@ -14,6 +14,9 @@
#include <VX_config.h>
#include "vx_scope.h"
#include "vortex_afu.h"
#include "scope-defs.h"
#define SCOPE_FRAME_WIDTH 1768
#define CHECK_RES(_expr) \
do { \
@@ -28,132 +31,6 @@
#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4)
#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4)
struct scope_signal_t {
int width;
const char* name;
};
constexpr int ilog2(int n) {
return (n > 1) ? 1 + ilog2(n >> 1) : 0;
}
static constexpr int NW_BITS = ilog2(NUM_WARPS);
#ifdef EXT_F_ENABLE
static constexpr int NR_BITS = ilog2(64);
#else
static constexpr int NR_BITS = ilog2(32);
#endif
static constexpr int EX_BITS = 3;
static constexpr int OP_BITS = 4;
static constexpr int MOD_BITS = 3;
static constexpr int ICORE_TAG_WIDTH = NW_BITS;
static constexpr int DCORE_TAG_WIDTH = ilog2(LSUQ_SIZE);
static constexpr scope_signal_t scope_signals[] = {
{ 32, "dram_req_addr" },
{ 1, "dram_req_rw" },
{ 16, "dram_req_byteen" },
{ 128, "dram_req_data" },
{ 29, "dram_req_tag" },
{ 128, "dram_rsp_data" },
{ 29, "dram_rsp_tag" },
{ 32, "snp_req_addr" },
{ 1, "snp_req_invalidate" },
{ 16, "snp_req_tag" },
{ 16, "snp_rsp_tag" },
{ NW_BITS, "icache_req_wid" },
{ 32, "icache_req_addr" },
{ ICORE_TAG_WIDTH, "icache_req_tag" },
{ 32, "icache_rsp_data" },
{ ICORE_TAG_WIDTH, "icache_rsp_tag" },
{ NW_BITS, "dcache_req_wid" },
{ 32, "dcache_req_pc" },
{ NUM_THREADS * 32, "dcache_req_addr" },
{ 1, "dcache_req_rw" },
{ NUM_THREADS * 4, "dcache_req_byteen" },
{ NUM_THREADS * 32, "dcache_req_data" },
{ DCORE_TAG_WIDTH, "dcache_req_tag" },
{ NUM_THREADS * 32, "dcache_rsp_data" },
{ DCORE_TAG_WIDTH, "dcache_rsp_tag" },
{ NW_BITS, "issue_wid" },
{ NUM_THREADS, "issue_tmask" },
{ 32, "issue_pc" },
{ EX_BITS, "issue_ex_type" },
{ OP_BITS, "issue_op_type" },
{ MOD_BITS, "issue_op_mod" },
{ 1, "issue_wb" },
{ NR_BITS, "issue_rd" },
{ NR_BITS, "issue_rs1" },
{ NR_BITS, "issue_rs2" },
{ NR_BITS, "issue_rs3" },
{ 32, "issue_imm" },
{ 1, "issue_rs1_is_pc" },
{ 1, "issue_rs2_is_imm" },
{ NW_BITS, "gpr_rsp_wid" },
{ 32, "gpr_rsp_pc" },
{ NUM_THREADS * 32, "gpr_rsp_a" },
{ NUM_THREADS * 32, "gpr_rsp_b" },
{ NUM_THREADS * 32, "gpr_rsp_c" },
{ NW_BITS, "writeback_wid" },
{ 32, "writeback_pc" },
{ NR_BITS, "writeback_rd" },
{ NUM_THREADS * 32, "writeback_data" },
{ 32, "bank_addr_st0" },
{ 32, "bank_addr_st1" },
{ 32, "bank_addr_st2" },
{ 1, "scope_bank_is_mrvq_st1" },
{ 1, "scope_bank_miss_st1" },
{ 1, "scope_bank_dirty_st1" },
{ 1, "scope_bank_force_miss_st1" },
///////////////////////////////////////////////////////////////////////////
{ 1, "dram_req_valid" },
{ 1, "dram_req_ready" },
{ 1, "dram_rsp_valid" },
{ 1, "dram_rsp_ready" },
{ 1, "snp_req_valid" },
{ 1, "snp_req_ready" },
{ 1, "snp_rsp_valid" },
{ 1, "snp_rsp_ready" },
{ 1, "icache_req_valid" },
{ 1, "icache_req_ready" },
{ 1, "icache_rsp_valid" },
{ 1, "icache_rsp_ready" },
{ NUM_THREADS, "dcache_req_valid" },
{ 1, "dcache_req_ready" },
{ NUM_THREADS, "dcache_rsp_valid" },
{ 1, "dcache_rsp_ready" },
{ 1, "bank_valid_st0" },
{ 1, "bank_valid_st1" },
{ 1, "bank_valid_st2" },
{ 1, "bank_stall_pipe" },
{ 1, "issue_valid" },
{ 1, "issue_ready" },
{ 1, "gpr_rsp_valid" },
{ 1, "writeback_valid" },
{ 1, "scoreboard_delay" },
{ 1, "gpr_delay" },
{ 1, "execute_delay" },
{ 1, "busy" },
};
static constexpr int num_signals = sizeof(scope_signals) / sizeof(scope_signal_t);
constexpr int calcFrameWidth(int index = 0) {
@@ -161,7 +38,6 @@ constexpr int calcFrameWidth(int index = 0) {
}
static constexpr int fwidth = calcFrameWidth();
static_assert(fwidth == 1766, "invalid size");
int vx_scope_start(fpga_handle hfpga, uint64_t delay) {
if (nullptr == hfpga)
@@ -190,9 +66,14 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
std::ofstream ofs("vx_scope.vcd");
ofs << "$version Generated by Vortex Scope $end" << std::endl;
ofs << "$timescale 1 ns $end" << std::endl;
ofs << "$var reg 1 0 clk $end" << std::endl;
for (int i = 0; i < num_signals; ++i) {
ofs << "$var reg " << scope_signals[i].width << " " << (i+1) << " " << scope_signals[i].name << " $end" << std::endl;
}
ofs << "enddefinitions $end" << std::endl;
uint64_t frame_width, max_frames, data_valid;
@@ -237,7 +118,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
ofs << "b1 0" << std::endl;
uint64_t delta;
fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta);
auto res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta);
assert(res == FPGA_OK);
while (delta != 0) {

2
driver/rtlsim/Makefile
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@@ -12,6 +12,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO

BIN
driver/tests/basic/kernel.bin
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Binary file not shown.

11
driver/tests/basic/kernel.dump
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@@ -74,7 +74,7 @@ Disassembly of section .text:
800000e0: 0005006b 0x5006b
800000e4: 00002197 auipc gp,0x2
800000e8: c8418193 addi gp,gp,-892 # 80001d68 <__global_pointer$>
800000ec: f14025f3 csrr a1,mhartid
800000ec: 022025f3 csrr a1,0x22
800000f0: 00a59593 slli a1,a1,0xa
800000f4: 02002673 csrr a2,0x20
800000f8: 00261613 slli a2,a2,0x2
@@ -122,7 +122,7 @@ Disassembly of section .text:
80000158: 00008067 ret
8000015c <vx_thread_gid>:
8000015c: f1402573 csrr a0,mhartid
8000015c: 02202573 csrr a0,0x22
80000160: 00008067 ret
80000164 <vx_core_id>:
@@ -458,13 +458,12 @@ Disassembly of section .comment:
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
0: 2041 jal 80 <_start-0x7fffff80>
0: 2541 jal 680 <_start-0x7ffff980>
2: 0000 unimp
4: 7200 flw fs0,32(a2)
6: 7369 lui t1,0xffffa
8: 01007663 bgeu zero,a6,14 <_start-0x7fffffec>
c: 0016 c.slli zero,0x5
e: 0000 unimp
c: 0000001b 0x1b
10: 1004 addi s1,sp,32
12: 7205 lui tp,0xfffe1
14: 3376 fld ft6,376(sp)
@@ -473,4 +472,4 @@ Disassembly of section .riscv.attributes:
1a: 5f30 lw a2,120(a4)
1c: 326d jal fffff9c6 <__global_pointer$+0x7fffdc5e>
1e: 3070 fld fa2,224(s0)
...
20: 665f 7032 0030 0x307032665f

BIN
driver/tests/basic/kernel.elf
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Binary file not shown.

2
hw/Makefile
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@@ -5,5 +5,5 @@ build_config:
$(MAKE) -C simulate
clean:
rm ./rtl/VX_user_config.vh ./VX_config.h
rm -f ./rtl/VX_user_config.vh ./VX_config.h
$(MAKE) -C simulate clean

90
hw/opae/vortex_afu.sv
View File

@@ -178,7 +178,7 @@ logic [31:0] cmd_csr_wdata;
t_ccip_c0_ReqMmioHdr mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
`IGNORE_WARNINGS_END
`STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, "Oops!")
`STATIC_ASSERT(($bits(t_ccip_c0_ReqMmioHdr)-$bits(mmio_hdr.address)) == 12, ("Oops!"))
t_if_ccip_c2_Tx mmio_tx;
assign af2cp_sTxPort.c2 = mmio_tx;
@@ -221,54 +221,54 @@ begin
MMIO_IO_ADDR: begin
cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_IO_ADDR: addr=%0h, data=0x%0h", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data));
`endif
end
MMIO_MEM_ADDR: begin
cmd_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_MEM_ADDR: addr=%0h, data=0x%0h", $time, mmio_hdr.address, t_local_mem_addr'(cp2af_sRxPort.c0.data));
`endif
end
MMIO_DATA_SIZE: begin
cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_DATA_SIZE: %0d", $time, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_DATA_SIZE: addr=%0h, data=%0d", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data));
`endif
end
MMIO_CMD_TYPE: begin
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CMD_TYPE: %0d", $time, $bits(cmd_type)'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_CMD_TYPE: addr=%0h, data=%0d", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data));
`endif
end
`ifdef SCOPE
MMIO_SCOPE_WRITE: begin
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_SCOPE_WRITE: %0h", $time, 64'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_SCOPE_WRITE: addr=%0h, data=%0h", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data));
`endif
end
`endif
MMIO_CSR_CORE: begin
cmd_csr_core <= $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CSR_CORE: %0h", $time, $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_CSR_CORE: addr=%0h, %0h", $time, mmio_hdr.address, $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data));
`endif
end
MMIO_CSR_ADDR: begin
cmd_csr_addr <= $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CSR_ADDR: %0h", $time, $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_CSR_ADDR: addr=%0h, %0h", $time, mmio_hdr.address, $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data));
`endif
end
MMIO_CSR_DATA: begin
cmd_csr_wdata <= $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CSR_DATA: %0h", $time, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data));
$display("%t: MMIO_CSR_DATA: addr=%0h, %0h", $time, mmio_hdr.address, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data));
`endif
end
default: begin
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_WR: addr=%0h, data=%0h", $time, mmio_hdr.address, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data));
$display("%t: Unknown MMIO Wr: addr=%0h, data=%0h", $time, mmio_hdr.address, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data));
`endif
end
endcase
@@ -297,27 +297,27 @@ begin
mmio_tx.data <= 64'(state);
`ifdef DBG_PRINT_OPAE
if (state != state_t'(mmio_tx.data)) begin
$display("%t: MMIO_STATUS: state=%0d", $time, state);
$display("%t: MMIO_STATUS: addr=%0h, state=%0d", $time, mmio_hdr.address, state);
end
`endif
end
MMIO_CSR_READ: begin
mmio_tx.data <= 64'(cmd_csr_rdata);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CSR_READ: data=%0h", $time, cmd_csr_rdata);
$display("%t: MMIO_CSR_READ: addr=%0h, data=%0h", $time, mmio_hdr.address, cmd_csr_rdata);
`endif
end
`ifdef SCOPE
MMIO_SCOPE_READ: begin
mmio_tx.data <= cmd_scope_rdata;
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_SCOPE_READ: data=%0h", $time, cmd_scope_rdata);
$display("%t: MMIO_SCOPE_READ: addr=%0h, data=%0h", $time, mmio_hdr.address, cmd_scope_rdata);
`endif
end
`endif
default: begin
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_RD: addr=%0h", $time, mmio_hdr.address);
$display("%t: Unknown MMIO Rd: addr=%0h", $time, mmio_hdr.address);
`endif
end
endcase
@@ -946,11 +946,15 @@ end
assign cmd_run_done = !vx_busy;
Vortex #() vortex (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_TOP_BIND
`SCOPE_SIGNALS_LSU_TOP_BIND
`SCOPE_SIGNALS_BANK_L3_TOP_BIND
`SCOPE_SIGNALS_BANK_L2_TOP_BIND
`SCOPE_SIGNALS_BANK_L1D_TOP_BIND
`SCOPE_SIGNALS_BANK_L1I_TOP_BIND
`SCOPE_SIGNALS_BANK_L1S_TOP_BIND
`SCOPE_SIGNALS_ISSUE_TOP_BIND
`SCOPE_SIGNALS_EXECUTE_TOP_BIND
.clk (clk),
.reset (reset | vx_reset),
@@ -1026,10 +1030,7 @@ end
`ifdef SCOPE
localparam SCOPE_DATAW = $bits({`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST});
localparam SCOPE_SR_DEPTH = 2;
`STATIC_ASSERT(SCOPE_DATAW == 1766, "invalid size")
localparam SCOPE_DATAW = $bits({`SCOPE_SIGNALS_DATA_LIST,`SCOPE_SIGNALS_UPD_LIST});
`SCOPE_ASSIGN (scope_dram_req_valid, vx_dram_req_valid);
`SCOPE_ASSIGN (scope_dram_req_addr, {vx_dram_req_addr, 4'b0});
@@ -1060,45 +1061,10 @@ localparam SCOPE_SR_DEPTH = 2;
`SCOPE_ASSIGN (scope_busy, vx_busy);
wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready)
|| (scope_icache_rsp_valid && scope_icache_rsp_ready)
|| ((| scope_dcache_req_valid) && scope_dcache_req_ready)
|| ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready)
|| (scope_dram_req_valid && scope_dram_req_ready)
|| (scope_dram_rsp_valid && scope_dram_rsp_ready)
|| (scope_snp_req_valid && scope_snp_req_ready)
|| (scope_snp_rsp_valid && scope_snp_rsp_ready)
|| (scope_issue_valid && scope_issue_ready)
|| scope_gpr_rsp_valid
|| scope_bank_valid_st0
|| scope_bank_valid_st1
|| scope_bank_valid_st2
|| scope_bank_stall_pipe
|| scope_scoreboard_delay
|| scope_gpr_delay
|| scope_execute_delay
|| scope_busy;
wire scope_changed = `SCOPE_TRIGGERS;
wire scope_start = vx_reset;
wire [SCOPE_DATAW+1:0] scope_data_in_st[SCOPE_SR_DEPTH-1:0];
wire [SCOPE_DATAW+1:0] scope_data_in_ste;
assign scope_data_in_st[0] = {`SCOPE_SIGNALS_DATA_LIST `SCOPE_SIGNALS_UPD_LIST, scope_changed, scope_start};
assign scope_data_in_ste = scope_data_in_st[SCOPE_SR_DEPTH-1];
for (genvar i = 1; i < SCOPE_SR_DEPTH; i++) begin
VX_generic_register #(
.N (SCOPE_DATAW+2)
) scope_sr (
.clk (clk),
.reset (reset),
.stall (0),
.flush (0),
.in (scope_data_in_st[i-1]),
.out (scope_data_in_st[i])
);
end
VX_scope #(
.DATAW (SCOPE_DATAW),
.BUSW (64),
@@ -1107,10 +1073,10 @@ VX_scope #(
) scope (
.clk (clk),
.reset (reset),
.start (scope_data_in_ste[0]),
.start (scope_start),
.stop (0),
.changed (scope_data_in_ste[1]),
.data_in (scope_data_in_ste[SCOPE_DATAW+1:2]),
.changed (scope_changed),
.data_in ({`SCOPE_SIGNALS_DATA_LIST,`SCOPE_SIGNALS_UPD_LIST}),
.bus_in (cmd_scope_wdata),
.bus_out (cmd_scope_rdata),
.bus_read (cmd_scope_read),

27
hw/rtl/VX_cluster.v
View File

@@ -3,11 +3,14 @@
module VX_cluster #(
parameter CLUSTER_ID = 0
) (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
`SCOPE_SIGNALS_ISTAGE_CLUSTER_IO
`SCOPE_SIGNALS_LSU_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L2_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_IO
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_IO
`SCOPE_SIGNALS_ISSUE_CLUSTER_IO
`SCOPE_SIGNALS_EXECUTE_CLUSTER_IO
// Clock
input wire clk,
@@ -138,11 +141,13 @@ module VX_cluster #(
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_SELECT(i)
`SCOPE_SIGNALS_LSU_SELECT(i)
`SCOPE_SIGNALS_BANK_L1D_CORE_SELECT(i)
`SCOPE_SIGNALS_BANK_L1I_CORE_SELECT(i)
`SCOPE_SIGNALS_BANK_L1S_CORE_SELECT(i)
`SCOPE_SIGNALS_ISSUE_SELECT(i)
`SCOPE_SIGNALS_EXECUTE_SELECT(i)
.clk (clk),
.reset (reset),
@@ -380,7 +385,7 @@ module VX_cluster #(
.SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH)
) l2cache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L2_CACHE_BIND
.clk (clk),
.reset (reset),

8
hw/rtl/VX_core.v
View File

@@ -5,7 +5,9 @@ module VX_core #(
) (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_L1D_CORE_IO
`SCOPE_SIGNALS_BANK_L1I_CORE_IO
`SCOPE_SIGNALS_BANK_L1S_CORE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
@@ -258,7 +260,9 @@ module VX_core #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_unit (
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_BANK_L1D_CORE_BIND
`SCOPE_SIGNALS_BANK_L1I_CORE_BIND
`SCOPE_SIGNALS_BANK_L1S_CORE_BIND
.clk (clk),
.reset (reset),

8
hw/rtl/VX_define.vh
View File

@@ -248,7 +248,7 @@
////////////////////////// Dcache Configurable Knobs //////////////////////////
// Cache ID
`define DCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 0)
`define DCACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0
// TAG sharing enable
`define DCORE_TAG_ID_BITS `LOG2UP(`LSUQ_SIZE)
@@ -277,7 +277,7 @@
////////////////////////// Icache Configurable Knobs //////////////////////////
// Cache ID
`define ICACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 1)
`define ICACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1
// Core request address bits
`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
@@ -309,7 +309,7 @@
////////////////////////// SM Configurable Knobs //////////////////////////////
// Cache ID
`define SCACHE_ID (((`L3_ENABLE && `L2_ENABLE) ? 2 : `L2_ENABLE ? 1 : 0) + (CORE_ID * 3) + 2)
`define SCACHE_ID 32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define SNUM_REQUESTS `NUM_THREADS
@@ -326,7 +326,7 @@
////////////////////////// L2cache Configurable Knobs /////////////////////////
// Cache ID
`define L2CACHE_ID (`L3_ENABLE ? 1 : 0)
`define L2CACHE_ID 32'(`L3_ENABLE) + CLUSTER_ID
// Core request tag bits
`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))

10
hw/rtl/VX_mem_unit.v
View File

@@ -3,7 +3,9 @@
module VX_mem_unit # (
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_L1D_CORE_IO
`SCOPE_SIGNALS_BANK_L1I_CORE_IO
`SCOPE_SIGNALS_BANK_L1S_CORE_IO
input wire clk,
input wire reset,
@@ -77,7 +79,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L1S_CACHE_BIND
.clk (clk),
.reset (reset),
@@ -159,7 +161,7 @@ module VX_mem_unit # (
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) dcache (
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_BANK_L1D_CACHE_BIND
.clk (clk),
.reset (reset),
@@ -240,7 +242,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) icache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L1I_CACHE_BIND
.clk (clk),
.reset (reset),

2
hw/rtl/VX_platform.vh
View File

@@ -41,7 +41,7 @@
`define STATIC_ASSERT(cond, msg) \
generate \
if (!(cond)) $error(msg); \
if (!(cond)) $error msg; \
endgenerate
`define ENABLE_TRACING /* verilator tracing_on */

465
hw/rtl/VX_scope.vh
View File

@@ -1,400 +1,89 @@
`ifndef VX_SCOPE
`define VX_SCOPE
`ifdef SCOPE
`define SCOPE_SIGNALS_DATA_LIST \
scope_dram_req_addr, \
scope_dram_req_rw, \
scope_dram_req_byteen, \
scope_dram_req_data, \
scope_dram_req_tag, \
scope_dram_rsp_data, \
scope_dram_rsp_tag, \
scope_snp_req_addr, \
scope_snp_req_invalidate, \
scope_snp_req_tag, \
scope_snp_rsp_tag, \
scope_icache_req_wid, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_wid, \
scope_dcache_req_pc, \
scope_dcache_req_addr, \
scope_dcache_req_rw, \
scope_dcache_req_byteen, \
scope_dcache_req_data, \
scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \
scope_issue_wid, \
scope_issue_tmask, \
scope_issue_pc, \
scope_issue_ex_type, \
scope_issue_op_type, \
scope_issue_op_mod, \
scope_issue_wb, \
scope_issue_rd, \
scope_issue_rs1, \
scope_issue_rs2, \
scope_issue_rs3, \
scope_issue_imm, \
scope_issue_rs1_is_pc, \
scope_issue_rs2_is_imm, \
scope_gpr_rsp_wid, \
scope_gpr_rsp_pc, \
scope_gpr_rsp_a, \
scope_gpr_rsp_b, \
scope_gpr_rsp_c, \
scope_writeback_wid, \
scope_writeback_pc, \
scope_writeback_rd, \
scope_writeback_data, \
scope_bank_addr_st0, \
scope_bank_addr_st1, \
scope_bank_addr_st2, \
scope_bank_is_mrvq_st1, \
scope_bank_miss_st1, \
scope_bank_dirty_st1, \
scope_bank_force_miss_st1,
`include "scope-defs.vh"
`define SCOPE_SIGNALS_UPD_LIST \
scope_dram_req_valid, \
scope_dram_req_ready, \
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_snp_req_valid, \
scope_snp_req_ready, \
scope_snp_rsp_valid, \
scope_snp_rsp_ready, \
scope_icache_req_valid, \
scope_icache_req_ready, \
scope_icache_rsp_valid, \
scope_icache_rsp_ready, \
scope_dcache_req_valid, \
scope_dcache_req_ready, \
scope_dcache_rsp_valid, \
scope_dcache_rsp_ready, \
scope_bank_valid_st0, \
scope_bank_valid_st1, \
scope_bank_valid_st2, \
scope_bank_stall_pipe, \
scope_issue_valid, \
scope_issue_ready, \
scope_gpr_rsp_valid, \
scope_writeback_valid, \
scope_scoreboard_delay, \
scope_gpr_delay, \
scope_execute_delay, \
scope_busy
`define SCOPE_ASSIGN(d,s) assign d = s
`define SCOPE_SIGNALS_DECL \
wire scope_dram_req_valid; \
wire [31:0] scope_dram_req_addr; \
wire scope_dram_req_rw; \
wire [15:0] scope_dram_req_byteen; \
wire [127:0] scope_dram_req_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
wire scope_dram_req_ready; \
wire scope_dram_rsp_valid; \
wire [127:0] scope_dram_rsp_data; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \
wire scope_snp_req_valid; \
wire [31:0] scope_snp_req_addr; \
wire scope_snp_req_invalidate; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_req_tag; \
wire scope_snp_req_ready; \
wire scope_snp_rsp_valid; \
wire [`VX_SNP_TAG_WIDTH-1:0] scope_snp_rsp_tag; \
wire scope_icache_req_valid; \
wire [`NW_BITS-1:0] scope_icache_req_wid; \
wire [31:0] scope_icache_req_addr; \
wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
wire [`NW_BITS-1:0] scope_dcache_req_wid; \
wire [31:0] scope_dcache_req_pc; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \
wire scope_dcache_req_rw; \
wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \
wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_snp_rsp_ready; \
wire [`NW_BITS-1:0] scope_issue_wid; \
wire [`NUM_THREADS-1:0] scope_issue_tmask; \
wire [31:0] scope_issue_pc; \
wire [`EX_BITS-1:0] scope_issue_ex_type; \
wire [`OP_BITS-1:0] scope_issue_op_type; \
wire [`MOD_BITS-1:0] scope_issue_op_mod; \
wire scope_issue_wb; \
wire [`NR_BITS-1:0] scope_issue_rd; \
wire [`NR_BITS-1:0] scope_issue_rs1; \
wire [`NR_BITS-1:0] scope_issue_rs2; \
wire [`NR_BITS-1:0] scope_issue_rs3; \
wire [31:0] scope_issue_imm; \
wire scope_issue_rs1_is_pc; \
wire scope_issue_rs2_is_imm; \
wire scope_gpr_rsp_valid; \
wire [`NW_BITS-1:0] scope_gpr_rsp_wid; \
wire [31:0] scope_gpr_rsp_pc; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b; \
wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c; \
wire scope_writeback_valid; \
wire [`NW_BITS-1:0] scope_writeback_wid; \
wire [31:0] scope_writeback_pc; \
wire [`NR_BITS-1:0] scope_writeback_rd; \
wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \
wire scope_bank_valid_st0; \
wire scope_bank_valid_st1; \
wire scope_bank_valid_st2; \
wire [31:0] scope_bank_addr_st0; \
wire [31:0] scope_bank_addr_st1; \
wire [31:0] scope_bank_addr_st2; \
wire scope_bank_is_mrvq_st1; \
wire scope_bank_miss_st1; \
wire scope_bank_dirty_st1; \
wire scope_bank_force_miss_st1; \
wire scope_bank_stall_pipe; \
wire scope_issue_valid; \
wire scope_issue_ready; \
wire scope_scoreboard_delay; \
wire scope_gpr_delay; \
wire scope_execute_delay; \
wire scope_busy;
`define SCOPE_SIGNALS_ISTAGE_IO \
output wire scope_icache_req_valid, \
output wire [`NW_BITS-1:0] scope_icache_req_wid, \
output wire [31:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_ID_BITS-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready,
`define SCOPE_SIGNALS_LSU_IO \
output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
output wire [`NW_BITS-1:0] scope_dcache_req_wid, \
output wire [31:0] scope_dcache_req_pc, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \
output wire scope_dcache_req_rw, \
output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \
output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \
output wire [`DCORE_TAG_ID_BITS-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready,
`define SCOPE_SIGNALS_CACHE_IO \
output wire scope_bank_valid_st0, \
output wire scope_bank_valid_st1, \
output wire scope_bank_valid_st2, \
output wire [31:0] scope_bank_addr_st0, \
output wire [31:0] scope_bank_addr_st1, \
output wire [31:0] scope_bank_addr_st2, \
output wire scope_bank_is_mrvq_st1, \
output wire scope_bank_miss_st1, \
output wire scope_bank_dirty_st1, \
output wire scope_bank_force_miss_st1, \
output wire scope_bank_stall_pipe,
`define SCOPE_SIGNALS_ISSUE_IO \
output wire scope_issue_valid, \
output wire [`NW_BITS-1:0] scope_issue_wid, \
output wire [`NUM_THREADS-1:0] scope_issue_tmask, \
output wire [31:0] scope_issue_pc, \
output wire [`EX_BITS-1:0] scope_issue_ex_type, \
output wire [`OP_BITS-1:0] scope_issue_op_type, \
output wire [`MOD_BITS-1:0] scope_issue_op_mod, \
output wire scope_issue_wb, \
output wire [`NR_BITS-1:0] scope_issue_rd, \
output wire [`NR_BITS-1:0] scope_issue_rs1, \
output wire [`NR_BITS-1:0] scope_issue_rs2, \
output wire [`NR_BITS-1:0] scope_issue_rs3, \
output wire [31:0] scope_issue_imm, \
output wire scope_issue_rs1_is_pc, \
output wire scope_issue_rs2_is_imm, \
output wire scope_writeback_valid, \
output wire scope_gpr_rsp_valid, \
output wire [`NW_BITS-1:0] scope_gpr_rsp_wid, \
output wire [31:0] scope_gpr_rsp_pc, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_a, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_b, \
output wire [`NUM_THREADS-1:0][31:0] scope_gpr_rsp_c, \
output wire [`NW_BITS-1:0] scope_writeback_wid, \
output wire [31:0] scope_writeback_pc, \
output wire [`NR_BITS-1:0] scope_writeback_rd, \
output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data, \
output wire scope_issue_ready, \
output wire scope_scoreboard_delay, \
output wire scope_gpr_delay, \
output wire scope_execute_delay,
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_wid (scope_icache_req_wid), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_LSU_BIND \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_wid (scope_dcache_req_wid), \
.scope_dcache_req_pc (scope_dcache_req_pc), \
.scope_dcache_req_addr (scope_dcache_req_addr), \
.scope_dcache_req_rw (scope_dcache_req_rw), \
.scope_dcache_req_byteen(scope_dcache_req_byteen), \
.scope_dcache_req_data (scope_dcache_req_data), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_data (scope_dcache_rsp_data), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_CACHE_BIND \
.scope_bank_valid_st0 (scope_bank_valid_st0), \
.scope_bank_valid_st1 (scope_bank_valid_st1), \
.scope_bank_valid_st2 (scope_bank_valid_st2), \
.scope_bank_addr_st0 (scope_bank_addr_st0), \
.scope_bank_addr_st1 (scope_bank_addr_st1), \
.scope_bank_addr_st2 (scope_bank_addr_st2), \
.scope_bank_is_mrvq_st1 (scope_bank_is_mrvq_st1), \
.scope_bank_miss_st1 (scope_bank_miss_st1), \
.scope_bank_dirty_st1 (scope_bank_dirty_st1), \
.scope_bank_force_miss_st1(scope_bank_force_miss_st1), \
.scope_bank_stall_pipe (scope_bank_stall_pipe),
`define SCOPE_SIGNALS_CACHE_UNBIND \
/* verilator lint_off PINCONNECTEMPTY */ \
.scope_bank_valid_st0 (), \
.scope_bank_valid_st1 (), \
.scope_bank_valid_st2 (), \
.scope_bank_addr_st0 (), \
.scope_bank_addr_st1 (), \
.scope_bank_addr_st2 (), \
.scope_bank_is_mrvq_st1 (), \
.scope_bank_miss_st1 (), \
.scope_bank_dirty_st1 (), \
.scope_bank_force_miss_st1 (), \
.scope_bank_stall_pipe (), \
/* verilator lint_on PINCONNECTEMPTY */
`define SCOPE_SIGNALS_CACHE_BANK_SELECT \
/* verilator lint_off UNUSED */ \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st0; \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_valid_st2; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st0; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st1; \
wire [NUM_BANKS-1:0][31:0] scope_per_bank_addr_st2; \
wire [NUM_BANKS-1:0] scope_per_bank_is_mrvq_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_dirty_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_force_miss_st1; \
wire [NUM_BANKS-1:0] scope_per_bank_stall_pipe; \
/* verilator lint_on UNUSED */ \
assign scope_bank_valid_st0 = scope_per_bank_valid_st0[0]; \
assign scope_bank_valid_st1 = scope_per_bank_valid_st1[0]; \
assign scope_bank_valid_st2 = scope_per_bank_valid_st2[0]; \
assign scope_bank_addr_st0 = scope_per_bank_addr_st0[0]; \
assign scope_bank_addr_st1 = scope_per_bank_addr_st1[0]; \
assign scope_bank_addr_st2 = scope_per_bank_addr_st2[0]; \
assign scope_bank_is_mrvq_st1 = scope_per_bank_is_mrvq_st1[0]; \
assign scope_bank_miss_st1 = scope_per_bank_miss_st1[0]; \
assign scope_bank_dirty_st1 = scope_per_bank_dirty_st1[0]; \
assign scope_bank_force_miss_st1 = scope_per_bank_force_miss_st1[0]; \
assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
`define SCOPE_SIGNALS_CACHE_BANK_BIND \
.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
`define SCOPE_SIGNALS_ISSUE_BIND \
.scope_issue_valid (scope_issue_valid), \
.scope_issue_wid (scope_issue_wid), \
.scope_issue_tmask (scope_issue_tmask), \
.scope_issue_pc (scope_issue_pc), \
.scope_issue_ex_type (scope_issue_ex_type), \
.scope_issue_op_type (scope_issue_op_type), \
.scope_issue_op_mod (scope_issue_op_mod), \
.scope_issue_wb (scope_issue_wb), \
.scope_issue_rd (scope_issue_rd), \
.scope_issue_rs1 (scope_issue_rs1), \
.scope_issue_rs2 (scope_issue_rs2), \
.scope_issue_rs3 (scope_issue_rs3), \
.scope_issue_imm (scope_issue_imm), \
.scope_issue_rs1_is_pc (scope_issue_rs1_is_pc), \
.scope_issue_rs2_is_imm (scope_issue_rs2_is_imm), \
.scope_writeback_valid (scope_writeback_valid), \
.scope_writeback_wid (scope_writeback_wid), \
.scope_writeback_pc (scope_writeback_pc), \
.scope_writeback_rd (scope_writeback_rd), \
.scope_writeback_data (scope_writeback_data), \
.scope_issue_ready (scope_issue_ready), \
.scope_gpr_rsp_valid (scope_gpr_rsp_valid), \
.scope_gpr_rsp_wid (scope_gpr_rsp_wid), \
.scope_gpr_rsp_pc (scope_gpr_rsp_pc), \
.scope_gpr_rsp_a (scope_gpr_rsp_a), \
.scope_gpr_rsp_b (scope_gpr_rsp_b), \
.scope_gpr_rsp_c (scope_gpr_rsp_c), \
.scope_scoreboard_delay (scope_scoreboard_delay), \
.scope_gpr_delay (scope_gpr_delay), \
.scope_execute_delay (scope_execute_delay), \
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_ASSIGN(d,s) assign d = s
`else
`define SCOPE_SIGNALS_ISTAGE_IO
`define SCOPE_SIGNALS_LSU_IO
`define SCOPE_SIGNALS_CACHE_IO
`define SCOPE_SIGNALS_ISSUE_IO
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND
`define SCOPE_SIGNALS_LSU_BIND
`define SCOPE_SIGNALS_CACHE_BIND
`define SCOPE_SIGNALS_ISSUE_BIND
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_SIGNALS_ISTAGE_TOP_IO
`define SCOPE_SIGNALS_ISTAGE_TOP_BIND
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_IO
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_BIND
`define SCOPE_SIGNALS_ISTAGE_IO
`define SCOPE_SIGNALS_ISTAGE_BIND
`define SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_ISTAGE_SELECT(__i__)
`define SCOPE_SIGNALS_LSU_TOP_IO
`define SCOPE_SIGNALS_LSU_TOP_BIND
`define SCOPE_SIGNALS_LSU_CLUSTER_IO
`define SCOPE_SIGNALS_LSU_CLUSTER_BIND
`define SCOPE_SIGNALS_LSU_IO
`define SCOPE_SIGNALS_LSU_BIND
`define SCOPE_SIGNALS_LSU_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_LSU_SELECT(__i__)
`define SCOPE_SIGNALS_ISSUE_TOP_IO
`define SCOPE_SIGNALS_ISSUE_TOP_BIND
`define SCOPE_SIGNALS_ISSUE_CLUSTER_IO
`define SCOPE_SIGNALS_ISSUE_CLUSTER_BIND
`define SCOPE_SIGNALS_ISSUE_IO
`define SCOPE_SIGNALS_ISSUE_BIND
`define SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_ISSUE_SELECT(__i__)
`define SCOPE_SIGNALS_EXECUTE_TOP_IO
`define SCOPE_SIGNALS_EXECUTE_TOP_BIND
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_IO
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_BIND
`define SCOPE_SIGNALS_EXECUTE_IO
`define SCOPE_SIGNALS_EXECUTE_BIND
`define SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_EXECUTE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L3_TOP_IO
`define SCOPE_SIGNALS_BANK_L3_TOP_BIND
`define SCOPE_SIGNALS_BANK_L2_TOP_IO
`define SCOPE_SIGNALS_BANK_L2_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1D_TOP_IO
`define SCOPE_SIGNALS_BANK_L1D_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1I_TOP_IO
`define SCOPE_SIGNALS_BANK_L1I_TOP_BIND
`define SCOPE_SIGNALS_BANK_L1S_TOP_IO
`define SCOPE_SIGNALS_BANK_L1S_TOP_BIND
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_IO
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_BIND
`define SCOPE_SIGNALS_BANK_L1D_CORE_IO
`define SCOPE_SIGNALS_BANK_L1D_CORE_BIND
`define SCOPE_SIGNALS_BANK_L1I_CORE_IO
`define SCOPE_SIGNALS_BANK_L1I_CORE_BIND
`define SCOPE_SIGNALS_BANK_L1S_CORE_IO
`define SCOPE_SIGNALS_BANK_L1S_CORE_BIND
`define SCOPE_SIGNALS_BANK_CACHE_IO
`define SCOPE_SIGNALS_BANK_CACHE_BIND
`define SCOPE_SIGNALS_BANK_IO
`define SCOPE_SIGNALS_BANK_BIND
`define SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1D_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1I_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L1S_CORE_SELECT(__i__)
`define SCOPE_SIGNALS_BANK_L3_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L2_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1D_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1I_CACHE_BIND
`define SCOPE_SIGNALS_BANK_L1S_CACHE_BIND
`define SCOPE_SIGNALS_BANK_SELECT(__i__)
`define SCOPE_ASSIGN(d,s)
`define SCOPE_SIGNALS_CACHE_UNBIND
`define SCOPE_SIGNALS_CACHE_BANK_SELECT
`define SCOPE_SIGNALS_CACHE_BANK_BIND
`define SCOPE_ASSIGN(d,s)
`endif
// VX_SCOPE
`endif

44
hw/rtl/Vortex.v
View File

@@ -1,11 +1,15 @@
`include "VX_define.vh"
module Vortex (
`SCOPE_SIGNALS_ISTAGE_IO
`SCOPE_SIGNALS_LSU_IO
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_ISSUE_IO
`SCOPE_SIGNALS_EXECUTE_IO
`SCOPE_SIGNALS_ISTAGE_TOP_IO
`SCOPE_SIGNALS_LSU_TOP_IO
`SCOPE_SIGNALS_BANK_L3_TOP_IO
`SCOPE_SIGNALS_BANK_L2_TOP_IO
`SCOPE_SIGNALS_BANK_L1D_TOP_IO
`SCOPE_SIGNALS_BANK_L1I_TOP_IO
`SCOPE_SIGNALS_BANK_L1S_TOP_IO
`SCOPE_SIGNALS_ISSUE_TOP_IO
`SCOPE_SIGNALS_EXECUTE_TOP_IO
// Clock
input wire clk,
@@ -75,11 +79,14 @@ module Vortex (
VX_cluster #(
.CLUSTER_ID(0)
) cluster (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_LSU_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(0)
`SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(0)
.clk (clk),
.reset (reset),
@@ -193,11 +200,14 @@ module Vortex (
VX_cluster #(
.CLUSTER_ID(i)
) cluster (
`SCOPE_SIGNALS_ISTAGE_BIND
`SCOPE_SIGNALS_LSU_BIND
`SCOPE_SIGNALS_CACHE_BIND
`SCOPE_SIGNALS_ISSUE_BIND
`SCOPE_SIGNALS_EXECUTE_BIND
`SCOPE_SIGNALS_ISTAGE_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_LSU_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L2_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1D_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1I_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_BANK_L1S_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_ISSUE_CLUSTER_SELECT(i)
`SCOPE_SIGNALS_EXECUTE_CLUSTER_SELECT(i)
.clk (clk),
.reset (reset),
@@ -384,7 +394,7 @@ module Vortex (
assign l3_core_rsp_ready = (& per_cluster_dram_rsp_ready);
VX_cache #(
.CACHE_ID (0),
.CACHE_ID (`L3CACHE_ID),
.CACHE_SIZE (`L3CACHE_SIZE),
.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
.NUM_BANKS (`L3NUM_BANKS),
@@ -407,7 +417,7 @@ module Vortex (
.SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH)
) l3cache (
`SCOPE_SIGNALS_CACHE_UNBIND
`SCOPE_SIGNALS_BANK_L3_CACHE_BIND
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_bank.v vendored
View File

@@ -50,7 +50,7 @@ module VX_bank #(
// Snooping request tag width
parameter SNP_REQ_TAG_WIDTH = 0
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_IO
input wire clk,
input wire reset,

6
hw/rtl/cache/VX_cache.v vendored
View File

@@ -59,7 +59,7 @@ module VX_cache #(
// Snooping forward tag width
parameter SNP_FWD_TAG_WIDTH = 1
) (
`SCOPE_SIGNALS_CACHE_IO
`SCOPE_SIGNALS_BANK_CACHE_IO
input wire clk,
input wire reset,
@@ -162,8 +162,6 @@ module VX_cache #(
wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
`SCOPE_SIGNALS_CACHE_BANK_SELECT
wire snp_req_valid_qual;
wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr_qual;
wire snp_req_invalidate_qual;
@@ -367,7 +365,7 @@ module VX_cache #(
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.SNP_REQ_TAG_WIDTH (SNP_REQ_TAG_WIDTH)
) bank (
`SCOPE_SIGNALS_CACHE_BANK_BIND
`SCOPE_SIGNALS_BANK_SELECT(i)
.clk (clk),
.reset (reset),

1
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -2,7 +2,6 @@
`define VX_CACHE_CONFIG
`include "VX_platform.vh"
`include "VX_scope.vh"
`ifdef DBG_CORE_REQ_INFO
`include "VX_define.vh"

2
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View File

@@ -66,7 +66,7 @@ module VX_cache_miss_resrv #(
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
`STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size")
`STATIC_ASSERT(MRVQ_SIZE > 5, ("invalid size"))
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -37,7 +37,7 @@ module VX_snp_forwarder #(
input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag,
output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
);
`STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value")
`STATIC_ASSERT(NUM_REQUESTS > 1, ("invalid value"))
reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];

2
hw/rtl/libs/VX_generic_queue.v
View File

@@ -17,7 +17,7 @@ module VX_generic_queue #(
output wire full,
output wire [SIZEW-1:0] size
);
`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
`STATIC_ASSERT(`ISPOW2(SIZE), ("must be 0 or power of 2!"))
reg [SIZEW-1:0] size_r;
wire reading;

48
hw/scripts/gen_synth_configs.py
View File

@@ -1,48 +0,0 @@
#!/usr/bin/env python3
import os
import glob
config_location = 'configs'
name_template = '{clusters}cl-{cores}c-{warps}w-{threads}t-{l2}Kl2-{dcache}Kd-{icache}Ki{name_suffix}.sh'
template = """
export V_NT={threads}
export V_NW={warps}
export V_NUM_CORES_PER_CLUSTER={cores}
export V_NUM_CLUSTERS={clusters}
export V_DCACHE_SIZE_BYTES={dcachek}
export V_ICACHE_SIZE_BYTES={icachek}
# L2 Cache size
export V_L2CACHE_SIZE_BYTES={l2k}
{codegen}
"""
# cluster, cores, warps, threads, l2, dcache, icache
configs = [
(1, 2, 8, 4, 8, 4, 1),
(1, 2, 8, 8, 8, 4, 1),
(1, 2, 8, 8, 16, 8, 1),
(1, 4, 8, 8, 16, 4, 1),
(1, 4, 8, 8, 16, 8, 1),
(1, 4, 16, 8, 16, 8, 1),
(2, 4, 8, 4, 8, 4, 1),
(2, 4, 8, 8, 16, 8, 1),
]
files = glob.glob(config_location + '/*.sh')
for f in files:
os.remove(f)
for clusters, cores, warps, threads, l2, dcache, icache in configs:
l2k, dcachek, icachek = 1024 * l2, 1024 * dcache, 1024 * icache
name_suffix = ''
with open(config_location + '/' + name_template.format(**locals()), 'w') as f:
codegen = ''
f.write(template.format(**locals()))

161
hw/scripts/scope.json Normal file
View File

@@ -0,0 +1,161 @@
{
"version": 1,
"includes":[
"../rtl/VX_config.vh",
"../rtl/VX_platform.vh",
"../rtl/VX_define.vh",
"../rtl/cache/VX_cache_config.vh"
],
"parameters": {
"L3_ENABLE": "`L3_ENABLE",
"L2_ENABLE": "`L2_ENABLE",
"NUM_CLUSTERS": "`NUM_CLUSTERS",
"NUM_CORES": "`NUM_CORES",
"DNUM_BANKS": "`DNUM_BANKS",
"INUM_BANKS": "`INUM_BANKS",
"SNUM_BANKS": "`SNUM_BANKS",
"L2NUM_BANKS": "`L2NUM_BANKS",
"L3NUM_BANKS": "`L3NUM_BANKS"
},
"taps": {
"top::SCOPE_SIGNALS_AFU": {
"!scope_dram_req_valid": 1,
"scope_dram_req_addr": 32,
"scope_dram_req_rw": 1,
"scope_dram_req_byteen": "`VX_DRAM_BYTEEN_WIDTH",
"scope_dram_req_data": "`VX_DRAM_LINE_WIDTH",
"scope_dram_req_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_req_ready": 1,
"!scope_dram_rsp_valid": 1,
"scope_dram_rsp_data": 128,
"scope_dram_rsp_tag": "`VX_DRAM_TAG_WIDTH",
"!scope_dram_rsp_ready": 1,
"!scope_snp_req_valid": 1,
"scope_snp_req_addr": 32,
"scope_snp_req_invalidate": 1,
"scope_snp_req_tag": "`VX_SNP_TAG_WIDTH",
"!scope_snp_req_ready": 1,
"!scope_snp_rsp_valid": 1,
"scope_snp_rsp_tag": "`VX_SNP_TAG_WIDTH",
"!scope_snp_rsp_ready": 1,
"scope_busy": 1
},
"core::SCOPE_SIGNALS_ISTAGE": {
"!scope_icache_req_valid": 1,
"scope_icache_req_wid": "`NW_BITS",
"scope_icache_req_addr": 32,
"scope_icache_req_tag": "`ICORE_TAG_ID_BITS",
"!scope_icache_req_ready": 1,
"!scope_icache_rsp_valid": 1,
"scope_icache_rsp_data": 32,
"scope_icache_rsp_tag": "`ICORE_TAG_ID_BITS",
"!scope_icache_rsp_ready": 1
},
"core::SCOPE_SIGNALS_LSU": {
"!scope_dcache_req_valid": "`NUM_THREADS",
"scope_dcache_req_wid": "`NW_BITS",
"scope_dcache_req_pc": 32,
"scope_dcache_req_addr": "`NUM_THREADS * 32",
"scope_dcache_req_rw": 1,
"scope_dcache_req_byteen": "`NUM_THREADS * 4",
"scope_dcache_req_data": "`NUM_THREADS * 32",
"scope_dcache_req_tag": "`DCORE_TAG_ID_BITS",
"!scope_dcache_req_ready": 1,
"!scope_dcache_rsp_valid": "`NUM_THREADS",
"scope_dcache_rsp_data": "`NUM_THREADS * 32",
"scope_dcache_rsp_tag": "`DCORE_TAG_ID_BITS",
"!scope_dcache_rsp_ready": 1
},
"core::SCOPE_SIGNALS_ISSUE": {
"!scope_issue_valid": 1,
"scope_issue_wid": "`NW_BITS",
"scope_issue_tmask": "`NUM_THREADS",
"scope_issue_pc": 32,
"scope_issue_ex_type": "`EX_BITS",
"scope_issue_op_type": "`OP_BITS",
"scope_issue_op_mod": "`MOD_BITS",
"scope_issue_wb": 1,
"scope_issue_rd": "`NR_BITS",
"scope_issue_rs1": "`NR_BITS",
"scope_issue_rs2": "`NR_BITS",
"scope_issue_rs3": "`NR_BITS",
"scope_issue_imm": 32,
"scope_issue_rs1_is_pc": 1,
"scope_issue_rs2_is_imm": 1,
"!scope_issue_ready": 1,
"!scope_gpr_rsp_valid": 1,
"scope_gpr_rsp_wid": "`NW_BITS",
"scope_gpr_rsp_pc": 32,
"scope_gpr_rsp_a": "`NUM_THREADS * 32",
"scope_gpr_rsp_b": "`NUM_THREADS * 32",
"scope_gpr_rsp_c": "`NUM_THREADS * 32",
"!scope_gpr_delay": 1,
"!scope_writeback_valid": 1,
"scope_writeback_wid": "`NW_BITS",
"scope_writeback_pc": 32,
"scope_writeback_rd": "`NR_BITS",
"scope_writeback_data": "`NUM_THREADS * 32",
"!scope_scoreboard_delay": 1,
"!scope_execute_delay": 1
},
"core::SCOPE_SIGNALS_EXECUTE": {},
"bank::SCOPE_SIGNALS_BANK": {
"!scope_bank_valid_st0": 1,
"!scope_bank_valid_st1": 1,
"!scope_bank_valid_st2": 1,
"scope_bank_addr_st0": 32,
"scope_bank_addr_st1": 32,
"scope_bank_addr_st2": 32,
"scope_bank_is_mrvq_st1": 1,
"scope_bank_miss_st1": 1,
"scope_bank_dirty_st1": 1,
"!scope_bank_force_miss_st1": 1,
"!scope_bank_stall_pipe": 1
}
},
"triggers": [
["scope_dram_req_valid", "scope_dram_req_ready"],
["scope_dram_rsp_valid", "scope_dram_rsp_ready"],
["scope_snp_req_valid", "scope_snp_req_ready"],
["scope_snp_rsp_valid", "scope_snp_rsp_ready"],
["scope_icache_req_valid_top", "scope_icache_req_ready_top"],
["scope_icache_rsp_valid_top", "scope_icache_rsp_ready_top"],
["scope_dcache_req_valid_top", "scope_dcache_req_ready_top"],
["scope_dcache_rsp_valid_top", "scope_dcache_rsp_ready_top"],
["scope_bank_valid_st0_l3_top"],
["scope_bank_valid_st1_l3_top"],
["scope_bank_valid_st2_l3_top"],
["scope_bank_stall_pipe_l3_top"],
["scope_bank_valid_st0_l2_top"],
["scope_bank_valid_st1_l2_top"],
["scope_bank_valid_st2_l2_top"],
["scope_bank_stall_pipe_l2_top"],
["scope_bank_valid_st0_l1d_top"],
["scope_bank_valid_st1_l1d_top"],
["scope_bank_valid_st2_l1d_top"],
["scope_bank_stall_pipe_l1d_top"],
["scope_bank_valid_st0_l1i_top"],
["scope_bank_valid_st1_l1i_top"],
["scope_bank_valid_st2_l1i_top"],
["scope_bank_stall_pipe_l1i_top"],
["scope_bank_valid_st0_l1s_top"],
["scope_bank_valid_st1_l1s_top"],
["scope_bank_valid_st2_l1s_top"],
["scope_bank_stall_pipe_l1s_top"],
["scope_issue_valid_top", "scope_issue_ready_top"],
["scope_gpr_rsp_valid_top"],
["scope_scoreboard_delay_top"],
["scope_gpr_delay_top"],
["scope_execute_delay_top"],
["scope_busy"]
]
}

630
hw/scripts/scope.py Executable file
View File

@@ -0,0 +1,630 @@
#!/usr/bin/env python3
import os
import re
import json
import argparse
import math
vl_include_re = re.compile(r"^\s*`include\s+\"(.+)\"")
vl_define_re = re.compile(r"^\s*`define\s+(\w+)(\([\w\s,]*\))?(.*)")
vl_ifdef_re = re.compile(r"^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$")
vl_endif_re = re.compile(r"^\s*`(endif|else)\s*$")
vl_expand_re = re.compile(r"`([0-9a-zA-Z_]+)")
parameters = []
exclude_files = []
include_dirs = []
macros = []
br_stack = []
def parse_func_args(text):
args = []
arg = ''
l = len(text)
if text[0] != '(':
raise Exception("missing leading parenthesis: " + text)
paren = 1
for i in range(1, l):
c = text[i]
if c == '(':
paren += 1
elif c == ')':
if paren == 0:
raise Exception("mismatched parenthesis: (" + i + ") " + text)
paren -= 1
if paren == 0:
l = i
break
if c == ',' and paren == 1:
if arg.strip():
args.append(arg)
arg = ''
else:
arg += c
if paren != 0:
raise Exception("missing closing parenthesis: " + text)
if arg.strip():
args.append(arg)
return (args, l)
def resolve_include_path(filename, parent_dir):
if os.path.basename(filename) in exclude_files:
return None
if os.path.isfile(filename):
return os.path.abspath(filename)
search_dirs = include_dirs
if parent_dir:
search_dirs.append(parent_dir)
for dir in search_dirs:
filepath = os.path.join(dir, filename)
if os.path.isfile(filepath):
return os.path.abspath(filepath)
raise Exception("couldn't find include file: " + filename)
def remove_comments(text):
text = re.sub(re.compile("/\*.*?\*/",re.DOTALL ), "", text) # multiline
text = re.sub(re.compile("//.*?\n" ), "\n", text) # singleline
return text
def add_macro(name, args, value):
macro = (name, args, value)
macros.append(macro)
if not args is None:
print("*** token: " + name + "(", end='')
for i in range(len(args)):
if i > 0:
print(', ', end='')
print(args[i], end='')
print(")=" + value)
else:
print("*** token: " + name + "=" + value)
def find_macro(name):
for macro in macros:
if macro[0] == name:
return macro
return None
def expand_text(text):
class DoRepl(object):
def __init__(self):
self.expanded = False
self.has_func = False
def __call__(self, match):
name = match.group(1)
macro = find_macro(name)
if macro:
if not macro[1] is None:
self.has_func = True
else:
self.expanded = True
return macro[2]
return "`" + name
class DoRepl2(object):
def __init__(self, args, f_args):
map = {}
for i in range(len(args)):
map[args[i]] = f_args[i]
self.map = map
def __call__(self, match):
for key in match.groups():
return self.map[key]
return group
def repl_func_macro(text):
expanded = False
match = re.search(vl_expand_re, text)
if match:
name = match.group(1)
macro = find_macro(name)
if macro:
args = macro[1]
value = macro[2]
if not args is None:
str_args = text[match.end():].strip()
f_args = parse_func_args(str_args)
if len(args) == 0:
if len(f_args[0]) != 0:
raise Exception("invalid argments for macro '" + name + "': value=" + text)
else:
if len(args) != len(f_args[0]):
raise Exception("mismatch number of argments for macro '" + name + "': actual=" + len(f_args[0]) + ", expected=" + len(args))
pattern = "(?<![0-9a-zA-Z_])("
for i in range(len(args)):
if i > 0:
pattern += "|"
pattern += args[i]
pattern += ")(?![0-9a-zA-Z_])"
dorepl = DoRepl2(args, f_args[0])
value = re.sub(pattern, dorepl, value)
str_head = text[0:match.start()]
str_tail = text[match.end() + f_args[1]+1:]
text = str_head + value + str_tail
expanded = True
if expanded:
return text
return None
changed = False
iter = 0
while True:
if iter > 99:
raise Exception("Macro recursion!")
has_func = False
while True:
do_repl = DoRepl()
new_text = re.sub(vl_expand_re, do_repl, text)
has_func = do_repl.has_func
if not do_repl.expanded:
break
text = new_text
changed = True
if not has_func:
break
expanded = repl_func_macro(text)
if not expanded:
break
text = expanded
changed = True
iter += 1
if changed:
return text
return None
def parse_include(filename, nesting):
if nesting > 99:
raise Exception("include recursion!")
print("*** parsing '" + filename + "'...")
content = None
with open(filename, "r") as f:
content = f.read()
# remove comments
content = remove_comments(content)
# parse content
prev_line = None
for line in content.splitlines(False):
# skip empty lines
if re.match(re.compile(r'^\s*$'), line):
continue
# merge multi-line lines
if line.endswith('\\'):
if prev_line:
prev_line += line[:len(line) - 1]
else:
prev_line = line[:len(line) - 1]
continue
if prev_line:
line = prev_line + line
prev_line = None
# parse ifdef
m = re.match(vl_ifdef_re, line)
if m:
key = m.group(1)
cond = m.group(2)
taken = find_macro(cond) is not None
if key == 'ifndef':
taken = not taken
elif key == '"elsif':
br_stack.pop()
br_stack.append(taken)
print("*** " + key + "(" + cond + ") => " + str(taken))
continue
# parse endif
m = re.match(vl_endif_re, line)
if m:
key = m.group(1)
top = br_stack.pop()
if key == 'else':
br_stack.append(not top)
print("*** " + key)
continue
# skip disabled blocks
if not all(br_stack):
continue
# parse include
m = re.match(vl_include_re, line)
if m:
include = m.group(1)
include = resolve_include_path(include, os.path.dirname(filename))
if include:
parse_include(include, nesting + 1)
continue
# parse define
m = re.match(vl_define_re, line)
if m:
name = m.group(1)
args = m.group(2)
if args:
args = args[1:len(args)-1].strip()
if args != '':
args = args.split(',')
for i in range(len(args)):
args[i] = args[i].strip()
else:
args = []
value = m.group(3)
add_macro(name, args, value.strip())
continue
def parse_includes(includes):
# change current directory to include directory
old_dir = os.getcwd()
script_dir = os.path.dirname(os.path.realpath(__file__))
os.chdir(script_dir)
for include in includes:
parse_include(include, 0)
# restore current directory
os.chdir(old_dir)
def load_include_dirs(dirs):
for dir in dirs:
print("*** include dir: " + dir)
include_dirs.append(dir)
def load_defines(defines):
for define in defines:
key_value = define.split('=', 2)
name = key_value[0]
value = ''
if len(key_value) == 2:
value = key_value[1]
add_macro(name, None, value)
def load_config(filename):
with open(filename, "r") as f:
config = json.load(f)
print("condfig=", config)
return config
def gen_cc_header(file, ports):
header = '''
#pragma once\n
struct scope_signal_t {
int width;
const char* name;
};\n
inline constexpr int __clog2(int n) { return (n > 1) ? 1 + __clog2((n + 1) >> 1) : 0; }\n
static constexpr scope_signal_t scope_signals[] = {'''
footer = "};"
def eval_macro(text):
expanded = expand_text(text)
if expanded:
text = expanded
text = text.replace('$clog2', '__clog2')
return text
def asize_name(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + "_" + str(i)
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
with open(file, 'w') as f:
print(header, file=f)
i = 0
for port in ports:
name = port[0]
size = eval_macro(str(port[1]))
for ss in asize_name(port[2]):
if i > 0:
print(",", file=f)
print("\t{" + size + ", \"" + name + ss + "\"}", file=f, end='')
i += 1
print("", file=f)
print(footer, file=f)
def gen_vl_header(file, taps, triggers):
header = '''
`ifndef VX_SCOPE_DEFS
`define VX_SCOPE_DEFS
'''
footer = '`endif'
def signal_size(size, asize):
str_asize = ""
for s in asize:
if type(s) == int:
str_asize += "[" + str(s-1) + ":0]"
else:
str_asize += "[" + str(s) + "-1:0]"
if type(size) == int:
size1 = (size-1)
if size1 != 0:
return str_asize + "[" + str(size1) + ":0]"
else:
return str_asize
else:
return str_asize + "[(" + size + ")-1:0]"
def generate_ports(tclass, tap, ports, new_taps):
def emit_io(tap, ports, prefix, asize, return_list, new_taps, is_enabled):
stap = tap + "_IO"
new_taps.append(stap)
print("`define " + stap + " \\", file=f)
if is_enabled:
for key in ports:
size = ports[key]
name = key
is_trigger = False
if name[0] == '!':
name = name[1:]
is_trigger = True
if not return_list is None:
return_list.append((name + prefix, size, asize, is_trigger))
print("\toutput wire" + signal_size(size, asize) + " " + name + prefix + ", \\", file=f)
print("", file=f)
emit_bind(tap, ports, prefix, prefix, new_taps, is_enabled)
def emit_bind(tap, ports, from_prefix, to_prefix, new_taps, is_enabled):
stap = tap + "_BIND"
new_taps.append(stap)
print("`define " + stap + " \\", file=f)
for key in ports:
name = key
if name[0] == '!':
name = name[1:]
if is_enabled:
print("\t." + name + to_prefix + " (" + name + from_prefix + "), \\", file=f)
else:
if (from_prefix != to_prefix):
print("\t`UNUSED_PIN (" + name + to_prefix + "), \\", file=f)
print("", file=f)
def emit_select(tap, ports, from_prefix, to_prefix, new_taps, is_enabled):
stap = tap + "_SELECT(__i__)"
new_taps.append(stap)
print("`define " + stap + " \\", file=f)
if is_enabled:
for key in ports:
name = key
if name[0] == '!':
name = name[1:]
print("\t." + name + to_prefix + " (" + name + from_prefix + "[__i__]), \\", file=f)
print("", file=f)
def do_top(tap, ports, new_taps):
out_ports = []
for p in ports:
name = p
is_trigger = False
if name[0] == '!':
name = name[1:]
is_trigger = True
out_ports.append((name, ports[p], [], is_trigger))
return out_ports
def do_core(tap, ports, new_taps):
out_ports = []
nclusters = parameters["NUM_CLUSTERS"]
ncores = parameters["NUM_CORES"]
emit_io(tap + "_TOP", ports, "_top", [nclusters, ncores], out_ports, new_taps, True)
emit_io(tap + "_CLUSTER", ports, "_cluster", [ncores], None, new_taps, True)
emit_io(tap + "", ports, "", [], None, new_taps, True)
emit_select(tap + "_CLUSTER", ports, "_top", "_cluster", new_taps, True)
emit_select(tap + "", ports, "_cluster", "", new_taps, True)
return out_ports
def do_bank(tap, ports, new_taps):
out_ports = []
nclusters = parameters["NUM_CLUSTERS"]
ncores = parameters["NUM_CORES"]
has_l3 = (parameters["L3_ENABLE"] != 0)
has_l2 = (parameters["L2_ENABLE"] != 0)
emit_io(tap + "_L3_TOP", ports, "_l3_cache", [parameters["L3NUM_BANKS"]], out_ports, new_taps, has_l3)
emit_io(tap + "_L2_TOP", ports, "_l2_top", [nclusters, parameters["L2NUM_BANKS"]], out_ports, new_taps, has_l2)
emit_io(tap + "_L1D_TOP", ports, "_l1d_top", [nclusters, ncores, parameters["DNUM_BANKS"]], out_ports, new_taps, True)
emit_io(tap + "_L1I_TOP", ports, "_l1i_top", [nclusters, ncores, parameters["INUM_BANKS"]], out_ports, new_taps, True)
emit_io(tap + "_L1S_TOP", ports, "_l1s_top", [nclusters, ncores, parameters["SNUM_BANKS"]], out_ports, new_taps, True)
emit_io(tap + "_L2_CLUSTER", ports, "_l2_cache", [parameters["L2NUM_BANKS"]], None, new_taps, has_l2)
emit_io(tap + "_L1D_CLUSTER", ports, "_l1d_cluster", [ncores, parameters["DNUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_L1I_CLUSTER", ports, "_l1i_cluster", [ncores, parameters["INUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_L1S_CLUSTER", ports, "_l1s_cluster", [ncores, parameters["SNUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_L1D_CORE", ports, "_l1d_cache", [parameters["DNUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_L1I_CORE", ports, "_l1i_cache", [parameters["INUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_L1S_CORE", ports, "_l1s_cache", [parameters["SNUM_BANKS"]], None, new_taps, True)
emit_io(tap + "_CACHE", ports, "_cache", ["NUM_BANKS"], None, new_taps, True)
emit_io(tap + "", ports, "", [], None, new_taps, True)
emit_select(tap + "_L2_CLUSTER", ports, "_l2_top", "_l2_cache", new_taps, has_l2)
emit_select(tap + "_L1D_CLUSTER", ports, "_l1d_top", "_l1d_cluster", new_taps, True)
emit_select(tap + "_L1I_CLUSTER", ports, "_l1i_top", "_l1i_cluster", new_taps, True)
emit_select(tap + "_L1S_CLUSTER", ports, "_l1s_top", "_l1s_cluster", new_taps, True)
emit_select(tap + "_L1D_CORE", ports, "_l1d_cluster", "_l1d_cache", new_taps, True)
emit_select(tap + "_L1I_CORE", ports, "_l1i_cluster", "_l1i_cache", new_taps, True)
emit_select(tap + "_L1S_CORE", ports, "_l1s_cluster", "_l1s_cache", new_taps, True)
emit_bind(tap + "_L3_CACHE", ports, "_l3_cache", "_cache", new_taps, has_l3)
emit_bind(tap + "_L2_CACHE", ports, "_l2_cache", "_cache", new_taps, has_l2)
emit_bind(tap + "_L1D_CACHE", ports, "_l1d_cache", "_cache", new_taps, True)
emit_bind(tap + "_L1I_CACHE", ports, "_l1i_cache", "_cache", new_taps, True)
emit_bind(tap + "_L1S_CACHE", ports, "_l1s_cache", "_cache", new_taps, True)
emit_select(tap + "", ports, "_cache", "", new_taps, True)
return out_ports
callbacks = {
"top": do_top,
"core": do_core,
"bank": do_bank
}
return callbacks[tclass](tap, ports, new_taps)
def trigger_size(name, ports):
for port in ports:
if port[0] == name:
return (port[1], port[2])
return None
def trigger_prefices(asize):
def Q(arr, ss, asize, idx, N):
for i in range(asize[idx]):
tmp = ss + '[' + str(i) + ']'
if (idx + 1) < N:
Q(arr, tmp, asize, idx + 1, N)
else:
arr.append(tmp)
l = len(asize)
if l == 0:
return [""]
arr = []
Q(arr, "", asize, 0, l)
return arr
def trigger_name(name, size):
if type(size) == int:
size1 = (size-1)
if size1 != 0:
return "(| " + name + ")"
else:
return name
else:
return "(| " + name + ")"
with open(file, 'w') as f:
print(header, file=f)
all_ports = []
new_taps = []
for key in taps:
[tclass, tap] = key.split('::')
ports = generate_ports(tclass, tap, taps[key], new_taps)
for port in ports:
all_ports.append(port)
print("`define SCOPE_SIGNALS_DECL \\", file=f)
i = 0
for port in all_ports:
if i > 0:
print(" \\", file=f)
print("\twire" + signal_size(port[1], port[2]) + " " + port[0] + ";", file=f, end='')
i += 1
print("", file=f)
print("", file=f)
print("`define SCOPE_SIGNALS_DATA_LIST \\", file=f)
i = 0
for port in all_ports:
if port[3]:
continue
if i > 0:
print(", \\", file=f)
print("\t" + port[0], file=f, end='')
i += 1
print("", file=f)
print("", file=f)
print("`define SCOPE_SIGNALS_UPD_LIST \\", file=f)
i = 0
for port in all_ports:
if not port[3]:
continue
if i > 0:
print(", \\", file=f)
print("\t" + port[0], file=f, end='')
i += 1
print("", file=f)
print("", file=f)
print("`define SCOPE_TRIGGERS \\", file=f)
i = 0
for trigger in triggers:
arr = trigger_size(trigger[0], all_ports)
if arr is None:
continue
[size, asize] = arr
for prefix in trigger_prefices(asize):
if i > 0:
print(" | \\", file=f)
print("\t(", file=f, end='')
for j in range(len(trigger)):
if j > 0:
print(" && ", file=f, end='')
print(trigger_name(trigger[j] + prefix, size), file=f, end='')
print(")", file=f, end='')
i += 1
print("", file=f)
print("", file=f)
print(footer, file=f)
return all_ports
def main():
parser = argparse.ArgumentParser(description='Scope headers generator.')
parser.add_argument('-vl', nargs='?', default='scope-defs.vh', metavar='file', help='Output Verilog header')
parser.add_argument('-cc', nargs='?', default='scope-defs.h', metavar='file', help='Output C++ header')
parser.add_argument('-D', nargs='?', action='append', metavar='macro[=value]', help='define macro')
parser.add_argument('-I', nargs='?', action='append', metavar='<includedir>', help='include directory')
parser.add_argument('config', help='Json config file')
args = parser.parse_args()
print("args=", args)
global parameters
global exclude_files
global include_dirs
global macros
global br_stack
if args.I:
load_include_dirs(args.I)
if args.D:
load_defines(args.D)
config = load_config(args.config)
exclude_files.append(os.path.basename(args.vl))
if "includes" in config:
parse_includes(config["includes"])
parameters = config["parameters"]
for key in parameters:
parameters[key] = int(eval(expand_text(str(parameters[key]))))
ports = gen_vl_header(args.vl, config["taps"], config["triggers"])
gen_cc_header(args.cc, ports)
if __name__ == "__main__":
main()

2
hw/simulate/Makefile
View File

@@ -13,6 +13,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSRQ
DBG_PRINT_FLAGS += -DDBG_PRINT_DRAM
DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_PRINT_FLAGS += -DDBG_CORE_REQ_INFO
DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO