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RTL refactoring

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This commit is contained in:
Blaise Tine
2020-04-21 07:13:56 -07:00
parent b6ce2dd3b8
commit 5798cf6e15
7 changed files with 39 additions and 32 deletions
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9
hw/opae/README
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@@ -36,4 +36,11 @@ export LD_LIBRARY_PATH=${PWD}:$LD_LIBRARY_PATH
cd /driver/tests/basic
make clean
make
./basic
./basic
ASE build instructions
vcd file vortex.vcd
vcd add -r /*/Vortex/hw/rtl/*
run -all

2
hw/opae/sources.txt
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@@ -70,7 +70,7 @@ vortex_afu.json
../rtl/VX_gpr.v
../rtl/VX_gpr_stage.v
../rtl/VX_dmem_ctrl.v
../rtl/VX_alu.v
../rtl/VX_alu_unit.v
../rtl/VX_csr_data.v
../rtl/VX_lsu.v
../rtl/VX_decode.v

2
hw/rtl/VX_alu.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_alu (
module VX_alu_unit (
input wire clk,
input wire reset,
input wire[31:0] src_a,

4
hw/rtl/VX_back_end.v
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@@ -70,7 +70,7 @@ VX_gpr_stage gpr_stage (
.gpr_stage_delay (gpr_stage_delay)
);
VX_lsu load_store_unit (
VX_lsu_unit lsu_unit (
.clk (clk),
.reset (reset),
.lsu_req_if (lsu_req_if),
@@ -109,7 +109,7 @@ VX_csr_pipe #(
.stall_gpr_csr(stall_gpr_csr)
);
VX_writeback wb (
VX_writeback writeback (
.clk (clk),
.reset (reset),
.mem_wb_if (mem_wb_if),

30
hw/rtl/VX_front_end.v
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@@ -37,8 +37,8 @@ module VX_front_end (
assign fetch_ebreak = vortex_ebreak || terminate_sim;
VX_wstall_if wstall_if();
VX_join_if join_if();
VX_wstall_if wstall_if();
VX_join_if join_if();
VX_fetch fetch(
.clk (clk),
@@ -59,11 +59,11 @@ module VX_front_end (
wire freeze_fi_reg = total_freeze || icache_stage_delay;
VX_f_d_reg f_i_reg(
.clk (clk),
.reset (reset),
.freeze (freeze_fi_reg),
.fe_inst_meta_fd(fe_inst_meta_fi),
.fd_inst_meta_de(fe_inst_meta_fi2)
.clk (clk),
.reset (reset),
.freeze (freeze_fi_reg),
.fe_inst_meta_fd (fe_inst_meta_fi),
.fd_inst_meta_de (fe_inst_meta_fi2)
);
VX_icache_stage icache_stage(
@@ -88,11 +88,11 @@ module VX_front_end (
);
VX_decode decode(
.fd_inst_meta_de (fd_inst_meta_de),
.frE_to_bckE_req_if (frE_to_bckE_req_if),
.wstall_if (wstall_if),
.join_if (join_if),
.terminate_sim (terminate_sim)
.fd_inst_meta_de (fd_inst_meta_de),
.frE_to_bckE_req_if (frE_to_bckE_req_if),
.wstall_if (wstall_if),
.join_if (join_if),
.terminate_sim (terminate_sim)
);
wire no_br_stall = 0;
@@ -101,9 +101,9 @@ module VX_front_end (
.clk (clk),
.reset (reset),
.branch_stall (no_br_stall),
.freeze (total_freeze),
.frE_to_bckE_req_if (frE_to_bckE_req_if),
.bckE_req_if (bckE_req_if)
.freeze (total_freeze),
.frE_to_bckE_req_if (frE_to_bckE_req_if),
.bckE_req_if (bckE_req_if)
);
endmodule

0
hw/rtl/VX_lsu.v → hw/rtl/VX_lsu_unit.v
View File

24
hw/rtl/Vortex.v
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@@ -147,28 +147,28 @@ assign gpu_dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
assign llc_snp_req_ready = gpu_dcache_snp_req_if.snp_req_ready;
VX_front_end front_end (
.clk (clk),
.clk (clk),
.reset (reset),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.schedule_delay (schedule_delay),
.icache_rsp_if (icache_rsp_if),
.icache_req_if (icache_req_if),
.jal_rsp_if (jal_rsp_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.fetch_ebreak (ebreak)
);
VX_scheduler schedule (
VX_scheduler scheduler (
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay),
.bckE_req_if (bckE_req_if),
.writeback_if (writeback_if),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
.reset (reset),
.memory_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay),
.bckE_req_if (bckE_req_if),
.writeback_if (writeback_if),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
);
VX_back_end #(
@@ -189,7 +189,7 @@ VX_back_end #(
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_ctrl dmem_controller (
VX_dmem_ctrl dmem_ctrl (
.clk (clk),
.reset (reset),