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Need to link SystemC for sc_time_stamp()

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This commit is contained in:
felsabbagh3
2019-10-14 23:25:14 -04:00
parent 22f02820cf
commit 8bc3b8b0a5
22 changed files with 958 additions and 372 deletions
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198
kernel/vortex_test.dump
View File

@@ -5,14 +5,14 @@ vortex_test.elf: file format elf32-littleriscv
Disassembly of section .text:
80000000 <_start>:
80000000: 00800513 li a0,8
80000004: 02051073 csrw 0x20,a0
80000008: 00400513 li a0,4
8000000c: 02151073 csrw 0x21,a0
80000010: f1401073 csrw mhartid,zero
80000014: 30101073 csrw misa,zero
80000018: 7ffff137 lui sp,0x7ffff
8000001c: 091010ef jal ra,800018ac <main>
80000000: 00200593 li a1,2
80000004: 00000013 nop
80000008: 00000013 nop
8000000c: 00000013 nop
80000010: 00058613 mv a2,a1
80000014: 00000013 nop
80000018: 00000013 nop
8000001c: 00000013 nop
80000020: 00000073 ecall
80000024 <vx_createThreads>:
@@ -28,7 +28,7 @@ Disassembly of section .text:
80000038: 00755c63 bge a0,t2,80000050 <loop_done>
8000003c <loop_body>:
8000003c: 80010113 addi sp,sp,-2048 # 7fffe800 <SIZE+0x7fffe7ce>
8000003c: 80010113 addi sp,sp,-2048
80000040: 00050313 mv t1,a0
80000044: 0003506b 0x3506b
@@ -1604,96 +1604,102 @@ Disassembly of section .text:
80001788: 03010113 addi sp,sp,48
8000178c: 00008067 ret
80001790 <initialize_mats>:
80001790: fe010113 addi sp,sp,-32
80001794: 00812e23 sw s0,28(sp)
80001798: 02010413 addi s0,sp,32
8000179c: fe042623 sw zero,-20(s0)
800017a0: 0480006f j 800017e8 <initialize_mats+0x58>
800017a4: 810267b7 lui a5,0x81026
800017a8: fec42703 lw a4,-20(s0)
800017ac: 00271713 slli a4,a4,0x2
800017b0: 21c78793 addi a5,a5,540 # 8102621c <barrier_bool+0xffffcf58>
800017b4: 00f707b3 add a5,a4,a5
800017b8: 00300713 li a4,3
800017bc: 00e7a023 sw a4,0(a5)
800017c0: 810277b7 lui a5,0x81027
800017c4: fec42703 lw a4,-20(s0)
800017c8: 00271713 slli a4,a4,0x2
800017cc: 21c78793 addi a5,a5,540 # 8102721c <barrier_bool+0xffffdf58>
800017d0: 00f707b3 add a5,a4,a5
800017d4: 00200713 li a4,2
800017d8: 00e7a023 sw a4,0(a5)
800017dc: fec42783 lw a5,-20(s0)
800017e0: 00178793 addi a5,a5,1
800017e4: fef42623 sw a5,-20(s0)
800017e8: fec42703 lw a4,-20(s0)
800017ec: 0ff00793 li a5,255
800017f0: fae7dae3 bge a5,a4,800017a4 <initialize_mats+0x14>
800017f4: 00000013 nop
800017f8: 01c12403 lw s0,28(sp)
800017fc: 02010113 addi sp,sp,32
80001800: 00008067 ret
80001790 <sc_time_stamp>:
80001790: ff010113 addi sp,sp,-16
80001794: 00812623 sw s0,12(sp)
80001798: 01010413 addi s0,sp,16
8000179c: 00000793 li a5,0
800017a0: 00000813 li a6,0
800017a4: 00078513 mv a0,a5
800017a8: 00080593 mv a1,a6
800017ac: 00c12403 lw s0,12(sp)
800017b0: 01010113 addi sp,sp,16
800017b4: 00008067 ret
80001804 <print_matrix>:
80001804: fd010113 addi sp,sp,-48
80001808: 02112623 sw ra,44(sp)
8000180c: 02812423 sw s0,40(sp)
80001810: 03010413 addi s0,sp,48
80001814: fca42e23 sw a0,-36(s0)
80001818: 810007b7 lui a5,0x81000
8000181c: 11878513 addi a0,a5,280 # 81000118 <barrier_bool+0xfffd6e54>
80001820: fb5fe0ef jal ra,800007d4 <vx_print_str>
80001824: fe042623 sw zero,-20(s0)
80001828: 0580006f j 80001880 <print_matrix+0x7c>
8000182c: fec42783 lw a5,-20(s0)
80001830: 00078e63 beqz a5,8000184c <print_matrix+0x48>
80001834: fec42783 lw a5,-20(s0)
80001838: 00f7f793 andi a5,a5,15
8000183c: 00079863 bnez a5,8000184c <print_matrix+0x48>
800017b8 <initialize_mats>:
800017b8: fe010113 addi sp,sp,-32
800017bc: 00812e23 sw s0,28(sp)
800017c0: 02010413 addi s0,sp,32
800017c4: fe042623 sw zero,-20(s0)
800017c8: 0480006f j 80001810 <initialize_mats+0x58>
800017cc: 810267b7 lui a5,0x81026
800017d0: fec42703 lw a4,-20(s0)
800017d4: 00271713 slli a4,a4,0x2
800017d8: 21c78793 addi a5,a5,540 # 8102621c <barrier_bool+0xffffcf58>
800017dc: 00f707b3 add a5,a4,a5
800017e0: 00300713 li a4,3
800017e4: 00e7a023 sw a4,0(a5)
800017e8: 810277b7 lui a5,0x81027
800017ec: fec42703 lw a4,-20(s0)
800017f0: 00271713 slli a4,a4,0x2
800017f4: 21c78793 addi a5,a5,540 # 8102721c <barrier_bool+0xffffdf58>
800017f8: 00f707b3 add a5,a4,a5
800017fc: 00200713 li a4,2
80001800: 00e7a023 sw a4,0(a5)
80001804: fec42783 lw a5,-20(s0)
80001808: 00178793 addi a5,a5,1
8000180c: fef42623 sw a5,-20(s0)
80001810: fec42703 lw a4,-20(s0)
80001814: 0ff00793 li a5,255
80001818: fae7dae3 bge a5,a4,800017cc <initialize_mats+0x14>
8000181c: 00000013 nop
80001820: 01c12403 lw s0,28(sp)
80001824: 02010113 addi sp,sp,32
80001828: 00008067 ret
8000182c <print_matrix>:
8000182c: fd010113 addi sp,sp,-48
80001830: 02112623 sw ra,44(sp)
80001834: 02812423 sw s0,40(sp)
80001838: 03010413 addi s0,sp,48
8000183c: fca42e23 sw a0,-36(s0)
80001840: 810007b7 lui a5,0x81000
80001844: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e78>
80001844: 11878513 addi a0,a5,280 # 81000118 <barrier_bool+0xfffd6e54>
80001848: f8dfe0ef jal ra,800007d4 <vx_print_str>
8000184c: fec42783 lw a5,-20(s0)
80001850: 00279793 slli a5,a5,0x2
80001854: fdc42703 lw a4,-36(s0)
80001858: 00f707b3 add a5,a4,a5
8000185c: 0007a783 lw a5,0(a5)
80001860: 00078513 mv a0,a5
80001864: fadfe0ef jal ra,80000810 <vx_print_hex>
8000184c: fe042623 sw zero,-20(s0)
80001850: 0580006f j 800018a8 <print_matrix+0x7c>
80001854: fec42783 lw a5,-20(s0)
80001858: 00078e63 beqz a5,80001874 <print_matrix+0x48>
8000185c: fec42783 lw a5,-20(s0)
80001860: 00f7f793 andi a5,a5,15
80001864: 00079863 bnez a5,80001874 <print_matrix+0x48>
80001868: 810007b7 lui a5,0x81000
8000186c: 14078513 addi a0,a5,320 # 81000140 <barrier_bool+0xfffd6e7c>
8000186c: 13c78513 addi a0,a5,316 # 8100013c <barrier_bool+0xfffd6e78>
80001870: f65fe0ef jal ra,800007d4 <vx_print_str>
80001874: fec42783 lw a5,-20(s0)
80001878: 00178793 addi a5,a5,1
8000187c: fef42623 sw a5,-20(s0)
80001880: fec42703 lw a4,-20(s0)
80001884: 0ff00793 li a5,255
80001888: fae7d2e3 bge a5,a4,8000182c <print_matrix+0x28>
8000188c: 810007b7 lui a5,0x81000
80001890: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e80>
80001894: f41fe0ef jal ra,800007d4 <vx_print_str>
80001898: 00000013 nop
8000189c: 02c12083 lw ra,44(sp)
800018a0: 02812403 lw s0,40(sp)
800018a4: 03010113 addi sp,sp,48
800018a8: 00008067 ret
80001878: 00279793 slli a5,a5,0x2
8000187c: fdc42703 lw a4,-36(s0)
80001880: 00f707b3 add a5,a4,a5
80001884: 0007a783 lw a5,0(a5)
80001888: 00078513 mv a0,a5
8000188c: f85fe0ef jal ra,80000810 <vx_print_hex>
80001890: 810007b7 lui a5,0x81000
80001894: 14078513 addi a0,a5,320 # 81000140 <barrier_bool+0xfffd6e7c>
80001898: f3dfe0ef jal ra,800007d4 <vx_print_str>
8000189c: fec42783 lw a5,-20(s0)
800018a0: 00178793 addi a5,a5,1
800018a4: fef42623 sw a5,-20(s0)
800018a8: fec42703 lw a4,-20(s0)
800018ac: 0ff00793 li a5,255
800018b0: fae7d2e3 bge a5,a4,80001854 <print_matrix+0x28>
800018b4: 810007b7 lui a5,0x81000
800018b8: 14478513 addi a0,a5,324 # 81000144 <barrier_bool+0xfffd6e80>
800018bc: f19fe0ef jal ra,800007d4 <vx_print_str>
800018c0: 00000013 nop
800018c4: 02c12083 lw ra,44(sp)
800018c8: 02812403 lw s0,40(sp)
800018cc: 03010113 addi sp,sp,48
800018d0: 00008067 ret
800018ac <main>:
800018ac: ff010113 addi sp,sp,-16
800018b0: 00112623 sw ra,12(sp)
800018b4: 00812423 sw s0,8(sp)
800018b8: 01010413 addi s0,sp,16
800018bc: ed5ff0ef jal ra,80001790 <initialize_mats>
800018c0: 810267b7 lui a5,0x81026
800018c4: 21c78513 addi a0,a5,540 # 8102621c <barrier_bool+0xffffcf58>
800018c8: f3dff0ef jal ra,80001804 <print_matrix>
800018cc: 00000793 li a5,0
800018d0: 00078513 mv a0,a5
800018d4: 00c12083 lw ra,12(sp)
800018d8: 00812403 lw s0,8(sp)
800018dc: 01010113 addi sp,sp,16
800018e0: 00008067 ret
800018d4 <main>:
800018d4: ff010113 addi sp,sp,-16
800018d8: 00812623 sw s0,12(sp)
800018dc: 01010413 addi s0,sp,16
800018e0: 00000793 li a5,0
800018e4: 00078513 mv a0,a5
800018e8: 00c12403 lw s0,12(sp)
800018ec: 01010113 addi sp,sp,16
800018f0: 00008067 ret
Disassembly of section .rodata:
@@ -1720,7 +1726,7 @@ Disassembly of section .rodata:
8100002a: 0000 unimp
8100002c: 0062 c.slli zero,0x18
8100002e: 0000 unimp
81000030: 00000063 beqz zero,81000030 <main+0xffe784>
81000030: 00000063 beqz zero,81000030 <main+0xffe75c>
81000034: 0064 addi s1,sp,12
81000036: 0000 unimp
81000038: 0065 c.nop 25
@@ -1757,7 +1763,7 @@ Disassembly of section .rodata:
8100007e: 0000 unimp
81000080: 0062 c.slli zero,0x18
81000082: 0000 unimp
81000084: 00000063 beqz zero,81000084 <main+0xffe7d8>
81000084: 00000063 beqz zero,81000084 <main+0xffe7b0>
81000088: 0064 addi s1,sp,12
8100008a: 0000 unimp
8100008c: 0065 c.nop 25
@@ -1788,7 +1794,7 @@ Disassembly of section .rodata:
810000c2: 0000 unimp
810000c4: 0062 c.slli zero,0x18
810000c6: 0000 unimp
810000c8: 00000063 beqz zero,810000c8 <main+0xffe81c>
810000c8: 00000063 beqz zero,810000c8 <main+0xffe7f4>
810000cc: 0064 addi s1,sp,12
810000ce: 0000 unimp
810000d0: 0065 c.nop 25
@@ -1817,7 +1823,7 @@ Disassembly of section .rodata:
81000102: 0000 unimp
81000104: 0062 c.slli zero,0x18
81000106: 0000 unimp
81000108: 00000063 beqz zero,81000108 <main+0xffe85c>
81000108: 00000063 beqz zero,81000108 <main+0xffe834>
8100010c: 0064 addi s1,sp,12
8100010e: 0000 unimp
81000110: 0065 c.nop 25

BIN
kernel/vortex_test.elf
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Binary file not shown.

49
kernel/vortex_test.hex
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@@ -1,6 +1,6 @@
:0200000480007A
:1000000013058000731005021305400073101502DC
:10001000731040F17310103037F1FF7FEF101009AB
:1000000093052000130000001300000013000000FF
:100010001386050013000000130000001300000009
:1000200073000000938B0600130D0700130F0100EF
:100030009303050013051000635C75001301018034
:10004000130305006B500300130515006FF0DFFE6E
@@ -376,28 +376,29 @@
:10176000B797028183C7472C93C7170093F7F70FEA
:10177000E39807FE13054006EFF01FEB130000008F
:101780008320C1020324810213010103678000004A
:10179000130101FE232E810013040102232604FEFF
:1017A0006F008004B76702810327C4FE1317270068
:1017B0009387C721B307F7001307300023A0E70082
:1017C000B77702810327C4FE131727009387C72129
:1017D000B307F7001307200023A0E7008327C4FE08
:1017E000938717002326F4FE0327C4FE9307F00F08
:1017F000E3DAE7FA130000000324C1011301010238
:1018000067800000130101FD2326110223248102B9
:1018100013040103232EA4FCB7070081138587114D
:10182000EFE05FFB232604FE6F0080058327C4FEE4
:10183000638E07008327C4FE93F7F70063980700C1
:10184000B70700811385C713EFE0DFF88327C4FED5
:10185000939727000327C4FDB307F70083A707006A
:1018600013850700EFE0DFFAB7070081138507143F
:10187000EFE05FF68327C4FE938717002326F4FE6C
:101880000327C4FE9307F00FE3D2E7FAB7070081FE
:1018900013854714EFE01FF4130000008320C102FA
:1018A000032481021301010367800000130101FF7B
:1018B000232611002324810013040101EFF05FEDC2
:1018C000B76702811385C721EFF0DFF393070000AC
:1018D000138507008320C100032481001301010147
:0418E000678000001D
:10179000130101FF232681001304010193070000B8
:1017A0001308000013850700930508000324C100F7
:1017B0001301010167800000130101FE232E810047
:1017C00013040102232604FE6F008004B767028120
:1017D0000327C4FE131727009387C721B307F70019
:1017E0001307300023A0E700B77702810327C4FE68
:1017F000131727009387C721B307F70013072000AB
:1018000023A0E7008327C4FE938717002326F4FE56
:101810000327C4FE9307F00FE3DAE7FA1300000092
:101820000324C1011301010267800000130101FDBF
:10183000232611022324810213040103232EA4FC76
:10184000B707008113858711EFE0DFF8232604FE38
:101850006F0080058327C4FE638E07008327C4FEC4
:1018600093F7F70063980700B70700811385C71344
:10187000EFE05FF68327C4FE939727000327C4FD9C
:10188000B307F70083A7070013850700EFE05FF8B1
:10189000B707008113850714EFE0DFF38327C4FE49
:1018A000938717002326F4FE0327C4FE9307F00F47
:1018B000E3D2E7FAB707008113854714EFE09FF101
:1018C000130000008320C1020324810213010103DD
:1018D00067800000130101FF23268100130401012A
:1018E00093070000138507000324C10013010101C1
:0418F000678000000D
:02000004810079
:10000000300000003100000032000000330000002A
:10001000340000003500000036000000370000000A

9
kernel/vx_main.c
View File

@@ -10,6 +10,11 @@ unsigned z[1024] = {0};
#define NUM_COLS 16
#define NUM_ROWS 16
double sc_time_stamp()
{
return 0;
}
void initialize_mats()
{
for (int i = 0; i < (MAT_DIM * MAT_DIM); i++)
@@ -36,14 +41,14 @@ int main()
// vx_print_hex(11);
initialize_mats();
// initialize_mats();
// matrix multiplication
// vx_sq_mat_mult(x, y, z, MAT_DIM);
// vx_print_str("\n\nMatrix multiplication\n");
// print_matrix(z);
print_matrix(x);
// print_matrix(x);
// // matrix addition
// vx_mat_add(x, y, z, NUM_ROWS, NUM_COLS);

30
kernel/vx_os/vx_back/vx_back.s
View File

@@ -6,19 +6,25 @@
.type _start, @function
.global _start
_start:
# li a1, 5
# jal Hi
# ecall
li a0, 8 # Num Warps
csrw 0x20, a0 # Setting the number of available warps
li a0, 4 # Num Threads
csrw 0x21, a0 # Setting the number of available threads
csrw mhartid,zero
csrw misa,zero
lui sp, 0x7ffff
# jal vx_before_main
jal main
li a1, 2
nop
nop
nop
addi a2, a1, 0
nop
nop
nop
ecall
# li a0, 8 # Num Warps
# csrw 0x20, a0 # Setting the number of available warps
# li a0, 4 # Num Threads
# csrw 0x21, a0 # Setting the number of available threads
# csrw mhartid,zero
# csrw misa,zero
# lui sp, 0x7ffff
# # jal vx_before_main
# jal main
# ecall
# Hi:
# li a2, 7

289
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp Normal file
View File

@@ -0,0 +1,289 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vrf2_32x128_wm1.h for the primary calling header
#include "Vrf2_32x128_wm1.h"
#include "Vrf2_32x128_wm1__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vrf2_32x128_wm1) {
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = __VlSymsp = new Vrf2_32x128_wm1__Syms(this, name());
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vrf2_32x128_wm1::__Vconfigure(Vrf2_32x128_wm1__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vrf2_32x128_wm1::~Vrf2_32x128_wm1() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void Vrf2_32x128_wm1::eval() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vrf2_32x128_wm1::eval\n"); );
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
#ifdef VL_DEBUG
// Debug assertions
_eval_debug_assertions();
#endif // VL_DEBUG
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
void Vrf2_32x128_wm1::_eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
// Evaluate till stable
int __VclockLoop = 0;
QData __Vchange = 1;
do {
_eval_settle(vlSymsp);
_eval(vlSymsp);
if (VL_UNLIKELY(++__VclockLoop > 100)) {
// About to fail, so enable debug to see what's not settling.
// Note you must run make with OPT=-DVL_DEBUG for debug prints.
int __Vsaved_debug = Verilated::debug();
Verilated::debug(1);
__Vchange = _change_request(vlSymsp);
Verilated::debug(__Vsaved_debug);
VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
} else {
__Vchange = _change_request(vlSymsp);
}
} while (VL_UNLIKELY(__Vchange));
}
//--------------------
// Internal Methods
VL_INLINE_OPT void Vrf2_32x128_wm1::_combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_combo__TOP__1\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at rf2_32x128_wm1.v:15356
if ((1U & (((~ (IData)(vlTOPp->CEN)) & (~ (IData)(vlTOPp->DFTRAMBYP)))
& (~ (IData)(vlTOPp->SE))))) {
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 0U;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = 0U;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U]
= vlTOPp->Q_in[0U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U]
= vlTOPp->Q_in[1U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U]
= vlTOPp->Q_in[2U];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U]
= vlTOPp->Q_in[3U];
while ((1U & (~ (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete)))) {
vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
= vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_table
[(0xfU & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i)];
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address
= (0xfU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 0xdU));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address
= (1U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 0xcU));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace
= (0x7fU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 5U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type
= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 3U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault
= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry
>> 1U));
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid
= (1U & vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry);
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i
= ((IData)(1U) + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i);
if (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid) {
if ((0U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault))) {
if ((((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address)
== (0xfU & ((IData)(vlTOPp->A)
>> 1U))) & ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address)
==
(1U
& (IData)(vlTOPp->A))))) {
if ((0x40U > (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
// Function: bit_error at rf2_32x128_wm1.v:15345
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]
= (((~ ((IData)(1U)
<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))))
& vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]) | (((0U
!= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type))
& ((1U
== (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type))
| (~
(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)
>> 5U)]
>>
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))))))
<<
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))));
} else {
if ((0x40U <= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
// Function: bit_error at rf2_32x128_wm1.v:15347
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type
= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]
= (((~ ((IData)(1U)
<< (0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))))
& vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]) |
(((0U != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type))
& ((1U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type))
| (~ (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)
>> 5U)]
>>
(0x1fU
& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))))))
<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))));
}
}
}
}
} else {
vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 1U;
}
}
vlTOPp->Q_out[0U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U];
vlTOPp->Q_out[1U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U];
vlTOPp->Q_out[2U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U];
vlTOPp->Q_out[3U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U];
} else {
vlTOPp->Q_out[0U] = vlTOPp->Q_in[0U];
vlTOPp->Q_out[1U] = vlTOPp->Q_in[1U];
vlTOPp->Q_out[2U] = vlTOPp->Q_in[2U];
vlTOPp->Q_out[3U] = vlTOPp->Q_in[3U];
}
}
void Vrf2_32x128_wm1::_eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_combo__TOP__1(vlSymsp);
}
void Vrf2_32x128_wm1::_eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_initial\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vrf2_32x128_wm1::final() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::final\n"); );
// Variables
Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp;
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vrf2_32x128_wm1::_eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_settle\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->_combo__TOP__1(vlSymsp);
}
VL_INLINE_OPT QData Vrf2_32x128_wm1::_change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_change_request\n"); );
Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
return __req;
}
#ifdef VL_DEBUG
void Vrf2_32x128_wm1::_eval_debug_assertions() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_eval_debug_assertions\n"); );
// Body
if (VL_UNLIKELY((CLK & 0xfeU))) {
Verilated::overWidthError("CLK");}
if (VL_UNLIKELY((A & 0xe0U))) {
Verilated::overWidthError("A");}
if (VL_UNLIKELY((CEN & 0xfeU))) {
Verilated::overWidthError("CEN");}
if (VL_UNLIKELY((DFTRAMBYP & 0xfeU))) {
Verilated::overWidthError("DFTRAMBYP");}
if (VL_UNLIKELY((SE & 0xfeU))) {
Verilated::overWidthError("SE");}
}
#endif // VL_DEBUG
void Vrf2_32x128_wm1::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vrf2_32x128_wm1::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,Q_out);
VL_RAND_RESET_W(128,Q_in);
CLK = VL_RAND_RESET_I(1);
A = VL_RAND_RESET_I(5);
CEN = VL_RAND_RESET_I(1);
DFTRAMBYP = VL_RAND_RESET_I(1);
SE = VL_RAND_RESET_I(1);
{ int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
rf2_32x128_wm1_error_injection__DOT__fault_table[__Vi0] = VL_RAND_RESET_I(17);
}}
rf2_32x128_wm1_error_injection__DOT__fault_entry = VL_RAND_RESET_I(17);
VL_RAND_RESET_W(128,__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = VL_RAND_RESET_I(32);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address = VL_RAND_RESET_I(4);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace = VL_RAND_RESET_I(7);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid = VL_RAND_RESET_I(1);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc = VL_RAND_RESET_I(7);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type = VL_RAND_RESET_I(2);
__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc = VL_RAND_RESET_I(7);
}

101
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vrf2_32x128_wm1_H_
#define _Vrf2_32x128_wm1_H_
#include "verilated.h"
class Vrf2_32x128_wm1__Syms;
//----------
VL_MODULE(Vrf2_32x128_wm1) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
// Begin mtask footprint all:
VL_IN8(CLK,0,0);
VL_IN8(A,4,0);
VL_IN8(CEN,0,0);
VL_IN8(DFTRAMBYP,0,0);
VL_IN8(SE,0,0);
VL_OUTW(Q_out,127,0,4);
VL_INW(Q_in,127,0,4);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_entry,16,0);
VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_table[16],16,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address,3,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace,6,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid,0,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc,6,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type,1,0);
VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc,6,0);
VL_SIGW(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output,127,0,4);
VL_SIG(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vrf2_32x128_wm1__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
VL_UNCOPYABLE(Vrf2_32x128_wm1); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible with respect to DPI scope names.
Vrf2_32x128_wm1(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vrf2_32x128_wm1();
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vrf2_32x128_wm1__Syms* symsp, bool first);
private:
static QData _change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset() VL_ATTR_COLD;
public:
static void _eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
static void _eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(128);
#endif // guard

53
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk Normal file
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vrf2_32x128_wm1.mk
default: Vrf2_32x128_wm1__ALL.a
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/local/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vrf2_32x128_wm1
# Module prefix (from --prefix)
VM_MODPREFIX = Vrf2_32x128_wm1
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
### Default rules...
# Include list of all generated classes
include Vrf2_32x128_wm1_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
# Verilated -*- Makefile -*-

19
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vrf2_32x128_wm1__Syms.h"
#include "Vrf2_32x128_wm1.h"
// FUNCTIONS
Vrf2_32x128_wm1__Syms::Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_didInit(false)
// Setup submodule names
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
}

35
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h Normal file
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header,
// unless using verilator public meta comments.
#ifndef _Vrf2_32x128_wm1__Syms_H_
#define _Vrf2_32x128_wm1__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vrf2_32x128_wm1.h"
// SYMS CLASS
class Vrf2_32x128_wm1__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_didInit;
// SUBCELL STATE
Vrf2_32x128_wm1* TOPp;
// CREATORS
Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep);
~Vrf2_32x128_wm1__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
} VL_ATTR_ALIGNED(64);
#endif // guard

1
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d Normal file
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@@ -0,0 +1 @@
obj_dir/Vrf2_32x128_wm1.cpp obj_dir/Vrf2_32x128_wm1.h obj_dir/Vrf2_32x128_wm1.mk obj_dir/Vrf2_32x128_wm1__Syms.cpp obj_dir/Vrf2_32x128_wm1__Syms.h obj_dir/Vrf2_32x128_wm1__ver.d obj_dir/Vrf2_32x128_wm1_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin rf2_32x128_wm1.v

12
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat Normal file
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@@ -0,0 +1,12 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-cc rf2_32x128_wm1.v"
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
T 14325 1013347 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.cpp"
T 4125 1013346 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.h"
T 1478 1013349 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1.mk"
T 570 1013345 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.cpp"
T 817 1013344 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__Syms.h"
T 292 1013350 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__ver.d"
T 0 0 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1__verFiles.dat"
T 1269 1013348 1571096194 0 1571096194 0 "obj_dir/Vrf2_32x128_wm1_classes.mk"
S 1252191 1011852 1571096122 0 1571096122 0 "rf2_32x128_wm1.v"

40
models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk Normal file
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@@ -0,0 +1,40 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vrf2_32x128_wm1.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 0
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
VM_TRACE_THREADED = 0
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vrf2_32x128_wm1 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vrf2_32x128_wm1__Syms \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

449
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
View File

@@ -56,6 +56,12 @@
`define ARM_MEM_HOLD 0.500
`define ARM_MEM_COLLISION 3.000
`define REALTIME 1
`undef POWER_PINS
`undef ARM_MESSAGES
/* verilator lint_off UNUSED */
module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q);
input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ;
output Q;
@@ -77,7 +83,7 @@ module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ
// model output side of RAM latch
always @(posedge Q_update or posedge XQ) begin
#0;
//#0;
if (XQ===1'b0) begin
if (DFTRAMBYP===1'b1)
Q=D_int;
@@ -97,7 +103,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
// ARM_UD_DP Defines the delay through Data Paths, for Memory Models it represents BIST MUX output delays.
`ifdef ARM_UD_DP
`else
`define ARM_UD_DP #0.001
`define ARM_UD_DP //#0.001
`endif
// ARM_UD_CP Defines the delay through Clock Path Cells, for Memory Models it is not used.
`ifdef ARM_UD_CP
@@ -107,7 +113,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
// ARM_UD_SEQ Defines the delay through the Memory, for Memory Models it is used for CLK->Q delays.
`ifdef ARM_UD_SEQ
`else
`define ARM_UD_SEQ #0.01
`define ARM_UD_SEQ //#0.01
`endif
`celldefine
@@ -1125,23 +1131,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
`ifdef INITIALIZE_MEMORY
integer i;
initial begin
#0;
//#0;
for (i = 0; i < MEM_HEIGHT; i = i + 1)
mem[i] = {MEM_WIDTH{1'b0}};
end
`endif
always @ (EMAA_) begin
if(EMAA_ < 3)
$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
end
always @ (EMASA_) begin
if(EMASA_ < 0)
$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
end
always @ (EMAB_) begin
if(EMAB_ < 3)
$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
end
// always @ (EMAA_) begin
// if(EMAA_ < 3)
// //$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0);
// end
// always @ (EMASA_) begin
// if(EMASA_ < 0)
// //$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0);
// end
// always @ (EMAB_) begin
// if(EMAB_ < 3)
// //$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0);
// end
task failedWrite;
input port_f;
@@ -1262,7 +1268,7 @@ task dumpmem;
reg [BITS-1:0] wordtemp;
reg [4:0] Atemp;
begin
dump_file_desc = $fopen(filename_dump);
dump_file_desc = $fopen(filename_dump, "w");
if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
for (i=0;i<WORDS;i=i+1) begin
Atemp = i;
@@ -1654,24 +1660,24 @@ task dumpaddr;
end
end
`ifdef POWER_PINS
always @ (VDDCE) begin
if (VDDCE != 1'b1) begin
if (VDDPE == 1'b1) begin
$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
end
$display("In PowerDown Mode in %m at %0t", $time);
failedWrite(0);
end
if (VDDCE == 1'b1) begin
if (VDDPE == 1'b1) begin
$display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
$display("Illegal power up sequencing in %m at %0t", $time);
end
failedWrite(0);
end
end
`endif
// `ifdef POWER_PINS
// always @ (VDDCE) begin
// if (VDDCE != 1'b1) begin
// if (VDDPE == 1'b1) begin
// //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0);
// end
// //$display("In PowerDown Mode in %m at %0t", 0);
// failedWrite(0);
// end
// if (VDDCE == 1'b1) begin
// if (VDDPE == 1'b1) begin
// //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0);
// //$display("Illegal power up sequencing in %m at %0t", 0);
// end
// failedWrite(0);
// end
// end
// `endif
`ifdef POWER_PINS
always @ (RET1N_ or VDDPE or VDDCE) begin
`else
@@ -1748,13 +1754,13 @@ task dumpaddr;
COLLDISN_int = 1'bx;
end
RET1N_int = RET1N_;
#0;
//#0;
QA_update = 1'b0;
#0;#0; XQA = 1'b0;
//#0;//#0; XQA = 1'b0;
end
always @ (CLKB_ or DFTRAMBYP_p2) begin
#0;
//#0;
if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
if (RET1N_ == 1'b1) begin
DB_sh_update = 1'b1;
@@ -1764,14 +1770,14 @@ task dumpaddr;
always @ CLKA_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
`endif
// `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// `endif
`ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else
@@ -1836,12 +1842,12 @@ task dumpaddr;
end
clk0_int = 1'b0;
ReadA;
if (CENA_int === 1'b0) previous_CLKA = $realtime;
#0;
if (CENA_int === 1'b0) previous_CLKA = `REALTIME;
//#0;
if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -1871,12 +1877,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -1884,30 +1890,30 @@ task dumpaddr;
end
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
`ifdef ARM_MESSAGES
$display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
// `endif
ROW_CC = 1;
`ifdef ARM_MESSAGES
$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end
end
@@ -2144,22 +2150,22 @@ task dumpaddr;
COLLDISN_int = 1'bx;
end
RET1N_int = RET1N_;
#0;
//#0;
QA_update = 1'b0;
DB_sh_update = 1'b0;
#0;#0; XDB_sh = 1'b0;
//#0;//#0; XDB_sh = 1'b0;
end
always @ CLKB_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
`endif
// `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// `endif
`ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else
@@ -2226,12 +2232,12 @@ task dumpaddr;
end else begin
WriteB;
end
if (CENB_int === 1'b0) previous_CLKB = $realtime;
#0;
if (CENB_int === 1'b0) previous_CLKB = `REALTIME;
//#0;
if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -2261,12 +2267,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -2274,30 +2280,30 @@ task dumpaddr;
end
end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
`ifdef ARM_MESSAGES
$display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
// `endif
ROW_CC = 1;
`ifdef ARM_MESSAGES
$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end
end
@@ -2444,16 +2450,16 @@ task dumpaddr;
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
always @ (VDDCE or VDDPE or VSSE) begin
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
end
`endif
// `ifdef POWER_PINS
// always @ (VDDCE or VDDPE or VSSE) begin
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// end
// `endif
function row_contention;
input [4:0] aa;
@@ -3612,23 +3618,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
`ifdef INITIALIZE_MEMORY
integer i;
initial begin
#0;
//#0;
for (i = 0; i < MEM_HEIGHT; i = i + 1)
mem[i] = {MEM_WIDTH{1'b0}};
end
`endif
always @ (EMAA_) begin
if(EMAA_ < 3)
$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
end
always @ (EMASA_) begin
if(EMASA_ < 0)
$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
end
always @ (EMAB_) begin
if(EMAB_ < 3)
$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
end
// always @ (EMAA_) begin
// if(EMAA_ < 3)
// //$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0);
// end
// always @ (EMASA_) begin
// if(EMASA_ < 0)
// //$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0);
// end
// always @ (EMAB_) begin
// if(EMAB_ < 3)
// //$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0);
// end
task failedWrite;
input port_f;
@@ -3749,7 +3755,7 @@ task dumpmem;
reg [BITS-1:0] wordtemp;
reg [4:0] Atemp;
begin
dump_file_desc = $fopen(filename_dump);
dump_file_desc = $fopen(filename_dump, "w");
if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
for (i=0;i<WORDS;i=i+1) begin
Atemp = i;
@@ -4141,24 +4147,24 @@ task dumpaddr;
end
end
`ifdef POWER_PINS
always @ (VDDCE) begin
if (VDDCE != 1'b1) begin
if (VDDPE == 1'b1) begin
$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
end
$display("In PowerDown Mode in %m at %0t", $time);
failedWrite(0);
end
if (VDDCE == 1'b1) begin
if (VDDPE == 1'b1) begin
$display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
$display("Illegal power up sequencing in %m at %0t", $time);
end
failedWrite(0);
end
end
`endif
// `ifdef POWER_PINS
// always @ (VDDCE) begin
// if (VDDCE != 1'b1) begin
// if (VDDPE == 1'b1) begin
// //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0);
// end
// //$display("In PowerDown Mode in %m at %0t", 0);
// failedWrite(0);
// end
// if (VDDCE == 1'b1) begin
// if (VDDPE == 1'b1) begin
// //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0);
// //$display("Illegal power up sequencing in %m at %0t", 0);
// end
// failedWrite(0);
// end
// end
// `endif
`ifdef POWER_PINS
always @ (RET1N_ or VDDPE or VDDCE) begin
`else
@@ -4235,13 +4241,13 @@ task dumpaddr;
COLLDISN_int = 1'bx;
end
RET1N_int = RET1N_;
#0;
//#0;
QA_update = 1'b0;
#0;#0; XQA = 1'b0;
//#0;//#0; XQA = 1'b0;
end
always @ (CLKB_ or DFTRAMBYP_p2) begin
#0;
//#0;
if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
if (RET1N_ == 1'b1) begin
DB_sh_update = 1'b1;
@@ -4251,14 +4257,14 @@ task dumpaddr;
always @ CLKA_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
`endif
// `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// `endif
`ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else
@@ -4323,12 +4329,12 @@ task dumpaddr;
end
clk0_int = 1'b0;
ReadA;
if (CENA_int === 1'b0) previous_CLKA = $realtime;
#0;
if (CENA_int === 1'b0) previous_CLKA = `REALTIME;
//#0;
if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4358,12 +4364,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4371,30 +4377,30 @@ task dumpaddr;
end
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
`ifdef ARM_MESSAGES
$display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
// `endif
ROW_CC = 1;
`ifdef ARM_MESSAGES
$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end
end
@@ -4413,7 +4419,7 @@ task dumpaddr;
initial cont_flag0_int = 1'b0;
always @ globalNotifier0 begin
if ($realtime == 0) begin
if (`REALTIME == 0) begin
end else if ((EMAA_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAA_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) ||
(EMAA_int[2] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMASA_int === 1'bx & DFTRAMBYP_int === 1'b1)
) begin
@@ -4436,7 +4442,7 @@ task dumpaddr;
AB_int, 1'b1, 1'b0)) begin
cont_flag0_int = 1'b0;
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4465,12 +4471,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4480,26 +4486,26 @@ task dumpaddr;
1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
cont_flag0_int = 1'b0;
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end
end else begin
#0;#0;
//#0;//#0;
ReadA;
end
#0;
//#0;
QA_update = 1'b0;
globalNotifier0 = 1'b0;
end
@@ -4727,22 +4733,22 @@ task dumpaddr;
COLLDISN_int = 1'bx;
end
RET1N_int = RET1N_;
#0;
//#0;
QA_update = 1'b0;
DB_sh_update = 1'b0;
#0;#0; XDB_sh = 1'b0;
//#0;//#0; XDB_sh = 1'b0;
end
always @ CLKB_ begin
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
`endif
// `ifdef POWER_PINS
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// `endif
`ifdef POWER_PINS
if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
`else
@@ -4809,12 +4815,12 @@ task dumpaddr;
end else begin
WriteB;
end
if (CENB_int === 1'b0) previous_CLKB = $realtime;
#0;
if (CENB_int === 1'b0) previous_CLKB = `REALTIME;
//#0;
if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4844,12 +4850,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4857,30 +4863,30 @@ task dumpaddr;
end
end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
AB_int, 1'b1, 1'b0)) begin
`ifdef ARM_MESSAGES
$display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
// `endif
ROW_CC = 1;
`ifdef ARM_MESSAGES
$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int
=== 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
`endif
// `ifdef ARM_MESSAGES
// //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
// `endif
READ_WRITE = 1;
end
end
@@ -4898,7 +4904,7 @@ task dumpaddr;
initial cont_flag1_int = 1'b0;
always @ globalNotifier1 begin
if ($realtime == 0) begin
if (`REALTIME == 0) begin
end else if ((EMAB_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAB_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) ||
(EMAB_int[2] === 1'bx & DFTRAMBYP_int === 1'b1)) begin
XDB_sh = 1'b1;
@@ -4924,7 +4930,7 @@ task dumpaddr;
AB_int, 1'b1, 1'b0)) begin
cont_flag1_int = 1'b0;
if((|WENB_int) == 1'b1) begin
$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4953,12 +4959,12 @@ task dumpaddr;
WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
WENB_int[2], WENB_int[1], WENB_int[0]};
mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
#0;
//#0;
QA_update = 1'b0;
#0;
//#0;
QA_update = 1'b1;
end else begin
$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
ROW_CC = 1;
COL_CC = 1;
READ_WRITE = 1;
@@ -4968,26 +4974,26 @@ task dumpaddr;
1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
cont_flag1_int = 1'b0;
ROW_CC = 1;
$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
READ_WRITE = 1;
DB_int = {128{1'bx}};
WriteB;
if (col_contention(AA_int,AB_int)) begin
$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
COL_CC = 1;
READ_WRITE = 1;
XQA = 1'b1; QA_update = 1'b1;
end else begin
`ifdef ARM_MESSAGES
$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
//$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
`endif
READ_WRITE = 1;
end
end else begin
#0;#0;
//#0;//#0;
WriteB;
end
#0;
//#0;
DB_sh_update = 1'b0;
globalNotifier1 = 1'b0;
end
@@ -5126,16 +5132,16 @@ task dumpaddr;
// If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
`ifdef POWER_PINS
always @ (VDDCE or VDDPE or VSSE) begin
if (VDDCE === 1'bx || VDDCE === 1'bz)
$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
if (VDDPE === 1'bx || VDDPE === 1'bz)
$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
if (VSSE === 1'bx || VSSE === 1'bz)
$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
end
`endif
// `ifdef POWER_PINS
// always @ (VDDCE or VDDPE or VSSE) begin
// if (VDDCE === 1'bx || VDDCE === 1'bz)
// //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
// if (VDDPE === 1'bx || VDDPE === 1'bz)
// //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
// if (VSSE === 1'bx || VSSE === 1'bz)
// //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
// end
// `endif
function row_contention;
input [4:0] aa;
@@ -15359,3 +15365,8 @@ begin
Q_out = Q_in;
end
endmodule
/* verilator lint_on UNUSED */

6
rtl/Makefile
View File

@@ -1,13 +1,13 @@
all: RUNFILE
# -LDFLAGS '-lsystemc'
VERILATOR:
echo "#define VCD_OFF" > tb_debug.h
verilator --compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint -cc Vortex.v -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -I/usr/local/systemc/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -O3' -LDFLAGS '-L/usr/local/systemc/'
compdebug:
echo "#define VCD_OUTPUT" > tb_debug.h
verilator --compiler gcc --prof-cfuncs -DVL_DEBUG=1 --coverage -Wall --trace -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG'
verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint --prof-cfuncs -DVL_DEBUG=1 --coverage --trace -cc Vortex.v -I/usr/local/systemc/ -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG' -LDFLAGS '-L/usr/local/systemc/'
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)

4
rtl/VX_decode.v
View File

@@ -33,9 +33,7 @@ module VX_decode(
assign VX_frE_to_bckE_req.curr_PC = in_curr_PC;
wire in_valid[`NT_M1:0];
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign in_valid[index] = fd_inst_meta_de.valid[index];
wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid;
wire[6:0] curr_opcode;

11
rtl/VX_gpr.v
View File

@@ -55,7 +55,11 @@ module VX_gpr (
// .q1 (out_b_reg_data)
// );
wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
// Port A is a read port, Port B is a write port
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
@@ -70,7 +74,7 @@ module VX_gpr (
.AA(VX_gpr_read.rs1),
.CLKB(clk),
.CENB(1'b0),
.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
@@ -92,7 +96,9 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 second_ram (
.CENYA(),
.AYA(),
@@ -107,7 +113,7 @@ module VX_gpr (
.AA(VX_gpr_read.rs2),
.CLKB(clk),
.CENB(1'b0),
.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
@@ -129,6 +135,7 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// >>>>>>> 5680b997b599ce2900997cab976681fe3881e880

6
rtl/VX_gpr_stage.v
View File

@@ -26,8 +26,10 @@ module VX_gpr_stage (
);
// wire[31:0] curr_PC = VX_bckE_req.curr_PC;
// wire[2:0] branchType = VX_bckE_req.branch_type;
wire[31:0] curr_PC = VX_bckE_req.curr_PC;
wire[2:0] branchType = VX_bckE_req.branch_type;
wire jalQual = VX_bckE_req.jalQual;
assign VX_fwd_req_de.src1 = VX_bckE_req.rs1;

6
rtl/byte_enabled_simple_dual_port_ram.v
View File

@@ -5,10 +5,10 @@
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input wire[4:0] waddr, raddr1,
input wire[4:0] waddr, raddr1, raddr2,
input wire[`NT_M1:0] be,
input wire[`NT_M1:0][31:0] wdata,
output reg[`NT_M1:0][31:0] q1
output reg[`NT_M1:0][31:0] q1, q2
);
// integer regi;
@@ -42,7 +42,7 @@ module byte_enabled_simple_dual_port_ram
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];

8
rtl/results.txt
View File

@@ -1,7 +1,7 @@
# Dynamic Instructions: 58157
# of total cycles: 58172
# Dynamic Instructions: 13
# of total cycles: 24
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00026
# time to simulate: 2.18459e-314 milliseconds
# CPI: 1.84615
# time to simulate: 6.95312e-310 milliseconds
# GRADE: Failed on test: 4294967295

2
rtl/tb_debug.h
View File

@@ -1 +1 @@
#define VCD_OFF
#define VCD_OUTPUT

2
rtl/test_bench.h
View File

@@ -376,7 +376,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// while (this->stats_total_cycles < 10)
{
// std::cout << "Counter: " << counter << "\n";
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
vortex->clk = 1;