Blaise Tine
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762b8e2e3e
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fixed cache mshr critical path
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2021-01-04 12:49:40 -05:00 |
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Blaise Tine
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4bc3b537bd
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fixed reset fan-out
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2021-01-03 20:06:36 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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30d950ada2
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vx_spawn_warps redesign using opencl's style scheduler
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2021-01-01 14:13:48 -05:00 |
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Blaise Tine
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138db29310
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2020-12-31 22:40:34 -05:00 |
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Blaise Tine
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e4a00dd0d9
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fixed loader script stack setup
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2020-12-31 22:37:20 -05:00 |
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Blaise Tine
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abe32ed553
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cache optimization - moved read requests to stage1 and eliminating stage3
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2020-12-31 07:40:58 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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4f689c4ce9
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fixed global obejct sharing between cores
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2020-12-24 19:36:07 -05:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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29cd2f5dff
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fixed register file initialization to zero synthesis inference
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2020-12-10 00:27:56 -08:00 |
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Blaise Tine
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707ba3760f
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minor update
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2020-12-08 21:37:53 -08:00 |
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Blaise Tine
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d5438fd591
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merging perf counters
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2020-12-08 21:02:39 -08:00 |
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Blaise Tine
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14baec86d5
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moved apae sources into rtl/afu
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2020-12-08 04:59:11 -08:00 |
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Blaise Tine
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d5fa82f5e4
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cache req datapath optimizations
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2020-12-08 02:58:08 -08:00 |
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Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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Blaise Tine
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d68b32cd60
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minor update
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2020-12-06 22:40:27 -08:00 |
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Blaise Tine
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b7a724410b
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update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
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2020-12-03 07:30:19 -08:00 |
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Blaise Tine
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b85391389b
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rename MSRQ to MSHR
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2020-11-28 17:32:00 -05:00 |
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Blaise Tine
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00d7473268
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build warnings clean
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2020-11-28 14:59:13 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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c04d385641
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minor update
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2020-11-23 20:12:04 -08:00 |
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Blaise Tine
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664ce28426
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minor update
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2020-11-23 12:21:39 -08:00 |
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Blaise Tine
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2d4fef6dd6
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fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
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2020-11-23 11:59:40 -08:00 |
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Blaise Tine
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20f22c7446
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scope minor fix
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2020-11-22 11:51:46 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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34b650be94
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fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
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2020-11-17 00:27:24 -08:00 |
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Blaise Tine
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61add25d96
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minor fix
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2020-11-16 08:23:16 -08:00 |
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Blaise Tine
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77bca2deca
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constant integration updates
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2020-11-16 02:39:53 -08:00 |
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Blaise Tine
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e946d976e7
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constant integration updates
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2020-11-15 08:44:57 -08:00 |
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Blaise Tine
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5d58bf3d11
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fixed l3cache hang using memory arbiter in afu
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2020-11-15 06:36:32 -08:00 |
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Blaise Tine
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2e0f51af80
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fixed instr/cycle perf counter
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2020-11-12 11:41:25 -08:00 |
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Blaise Tine
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ce95c40aee
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fixed redundant cache fills
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2020-11-11 12:07:27 -05:00 |
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Blaise Tine
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0bacfd2dae
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minor update
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2020-11-10 13:47:28 -05:00 |
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Blaise Tine
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725322807e
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fixed DRAM response backpressure inside Cache
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2020-11-10 05:24:57 -08:00 |
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Blaise Tine
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ed69be4027
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pipeline optimization: fixed GPR fanout delay to execute unitsddddssssvcd
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2020-11-09 21:41:06 -08:00 |
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Blaise Tine
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7c384eaf7f
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fixed snoop forwarding hang
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2020-11-09 20:02:33 -08:00 |
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Blaise Tine
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f8d54c6994
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fixed cache_core_rsp_merge unit
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2020-11-09 02:10:35 -08:00 |
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Blaise Tine
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10505caae1
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refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
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2020-11-08 01:31:46 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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3fe31fc337
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fixed afu to cpu mempcy hang
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2020-10-28 14:19:13 -07:00 |
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Blaise Tine
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9a9f7955f0
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basic test timing + scope tracing ccip
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2020-10-27 17:04:04 -04:00 |
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Blaise Tine
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4bd5ee2673
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fixed rtlsim regression
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2020-10-26 12:59:58 -04:00 |
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Blaise Tine
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09b1c0eea7
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minor update
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2020-10-26 02:02:05 -07:00 |
|
Blaise Tine
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48897d9778
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minor update
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2020-10-25 18:29:25 -07:00 |
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Blaise Tine
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43ae82e788
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vlsim fix, verilator fst trace, use ram optimization
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2020-10-25 16:40:50 -07:00 |
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Blaise Tine
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81dc8c7279
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minor update
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2020-10-20 16:47:01 -04:00 |
|
Blaise Tine
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8290ad8828
|
minor update
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2020-10-20 05:49:45 -07:00 |
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