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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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47c3234659
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minor update
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2021-06-13 10:58:48 -07:00 |
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8bf85c1983
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fixed non-cacheable memory with l2 cache
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2021-06-10 15:11:37 -07:00 |
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adf033b0aa
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non-cacheable memory address critical paths optimizations
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2021-06-10 12:47:18 -07:00 |
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41069ba188
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non-cacheable memory address fixes
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2021-06-06 20:54:36 -07:00 |
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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4c5104e96a
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fixed shared memory multi-tag requests bug
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2021-05-26 15:03:48 -07:00 |
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d8517d4d08
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minor update
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2021-05-26 13:37:07 -07:00 |
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244f4b0964
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fixed shared memory write bug
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2021-05-23 10:57:58 -07:00 |
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04a1c0e9eb
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IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
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2021-05-01 13:44:08 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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625689796f
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minor update
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2021-04-04 23:42:57 -07:00 |
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d6552a8851
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minor update
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2021-04-03 04:24:37 -07:00 |
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04a96e89c9
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minor update
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2021-04-01 12:34:18 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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1346d64ba9
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minor update
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2021-02-22 04:04:13 -08:00 |
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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fd1726197b
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cache merge optimization
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2021-02-07 07:33:39 -08:00 |
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111cc29482
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minor update
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2021-02-04 15:28:04 -08:00 |
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32b94f61f2
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minor update
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2021-02-01 11:00:09 -08:00 |
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62ff97d6e1
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minor update - smem perf update
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2021-02-01 10:29:20 -08:00 |
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dc18bfabb8
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minor update - remove mshr data store
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2021-01-30 06:40:48 -08:00 |
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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74a687e395
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minor updates
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2021-01-18 05:43:30 -08:00 |
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b17f1109c6
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minor updates
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2021-01-18 04:34:34 -08:00 |
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a7f6b9fffc
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minor updates
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2021-01-17 18:18:05 -08:00 |
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8b42393189
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minor updates
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2021-01-17 17:33:41 -08:00 |
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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a69ba5ad7b
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cache flush support
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2021-01-17 05:50:29 -08:00 |
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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5b80484123
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minor updates
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2021-01-16 14:16:10 -08:00 |
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Blaise Tine
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a56ecb696d
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minor updates
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2021-01-16 14:05:47 -08:00 |
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4f26228d50
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minor updates
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2021-01-16 05:33:28 -08:00 |
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