felsabbagh3
|
b99ba2c413
|
Removed scheduler_empty qualifier
|
2020-03-29 15:24:50 -07:00 |
|
felsabbagh3
|
efac643c66
|
Added Proper Handshaking to Everything and Fixed a Couple of Bugs
|
2020-03-29 02:11:14 -07:00 |
|
felsabbagh3
|
313a8e3b4b
|
All cache bugs fixed - Handshaking
|
2020-03-28 21:43:02 -07:00 |
|
felsabbagh3
|
5dc9493c61
|
ALL tests passing - handshake
|
2020-03-27 21:34:49 -07:00 |
|
Blaise Tine
|
e80fa7f233
|
missing rtl changes from OPAE
|
2020-03-27 22:37:35 -04:00 |
|
Blaise Tine
|
a7eb9a0c38
|
code refactoring
|
2020-03-26 03:20:46 -04:00 |
|
Blaise Tine
|
4626389ee2
|
code refactoring
|
2020-03-26 01:41:01 -04:00 |
|
felsabbagh3
|
13c6cbfa5d
|
L3 and CLUSTRING WORKS
|
2020-03-10 02:41:47 -07:00 |
|
felsabbagh3
|
e2ffbcf14b
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
felsabbagh3
|
2f94b26af0
|
Icache working
|
2020-03-08 13:59:35 -07:00 |
|
felsabbagh3
|
507d20f413
|
Cache Working on Mem Copy
|
2020-03-08 01:55:15 -08:00 |
|
felsabbagh3
|
9bf0add937
|
Made the cache module configurable for multi-instantiation
|
2020-03-07 00:49:40 -08:00 |
|
Blaise Tine
|
66a46f81ce
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
felsabbagh3
|
b0b9b8238e
|
Passing some cases
|
2020-03-04 04:05:54 -08:00 |
|
felsabbagh3
|
8f001ac6f2
|
Added All Interfaces
|
2020-03-03 22:48:49 -08:00 |
|
felsabbagh3
|
73cecd3866
|
Added Core Interface
|
2020-03-03 22:14:56 -08:00 |
|
wgulian3
|
61803741f8
|
Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
|
2020-02-18 03:34:38 -05:00 |
|
felsabbagh3
|
3a45375596
|
Fixed Verilator
|
2020-02-17 19:36:00 -08:00 |
|
wgulian3
|
8318aff69f
|
Support exec multi-cycle for div/mul
|
2020-02-13 13:17:46 -05:00 |
|
wgulian3
|
8d20b52ea2
|
Cleanup imports of VX_define
|
2020-02-04 10:57:32 -05:00 |
|
wgulian3
|
e9cdc6e5af
|
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
|
2020-01-24 06:10:24 -05:00 |
|
Lyons, Ethan Tyler
|
b0f685c2e2
|
Add files via upload
ICache_In_Place
|
2019-11-08 10:55:08 -05:00 |
|
Savan Roshan
|
e4ee2a9cbd
|
Parameterization working
|
2019-11-07 00:14:46 -05:00 |
|
Savan Roshan
|
8468e7d4d9
|
Added prefix DCACHE_
|
2019-11-05 08:33:38 -05:00 |
|
Savan Roshan
|
1db160a289
|
Fixed parameterization
|
2019-11-04 14:32:02 -05:00 |
|
felsabbagh3
|
3b49b82c46
|
GPR ASIC Working
|
2019-10-29 23:20:16 -04:00 |
|
felsabbagh3
|
a8d063e9ad
|
Synthesis Cleanup 1
|
2019-10-28 13:43:12 -04:00 |
|
felsabbagh3
|
0ee74bc566
|
migrated 100% to modelsim
|
2019-10-27 20:08:44 -04:00 |
|
felsabbagh3
|
1181af1df2
|
Modelsim basic sim
|
2019-10-26 00:34:57 -04:00 |
|
felsabbagh3
|
01efe02e8b
|
CACHE WORKING just needs lb/sb
|
2019-10-25 03:03:09 -04:00 |
|
felsabbagh3
|
1e648c5819
|
FIxed first circular issue
|
2019-10-24 10:38:04 -04:00 |
|
felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
|
2019-10-22 06:02:08 -04:00 |
|
felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
felsabbagh3
|
1bfafca896
|
Cleanup before integration
|
2019-10-22 03:03:17 -04:00 |
|
felsabbagh3
|
0672389edc
|
fix
|
2019-10-21 12:16:17 -04:00 |
|
felsabbagh3
|
84f5ccb484
|
Added CSR TID/WID reads
|
2019-10-21 02:10:05 -04:00 |
|
felsabbagh3
|
629ed3f8f9
|
Before ISA2.0
|
2019-10-18 04:15:34 -04:00 |
|
felsabbagh3
|
559c64cb36
|
Cleanup
|
2019-10-18 02:20:38 -04:00 |
|
felsabbagh3
|
505bbc20c8
|
Removed FWD
|
2019-10-18 02:01:39 -04:00 |
|
felsabbagh3
|
95047fcadc
|
Rename Stage that removes the need for forwarding
|
2019-10-17 00:48:54 -04:00 |
|
felsabbagh3
|
ee83e6d8c8
|
Moved GPR to back-end
|
2019-10-14 19:08:32 -04:00 |
|
felsabbagh3
|
fb3bc60189
|
Finalized GPR with 3-Port Structure
|
2019-09-11 14:53:32 -04:00 |
|
felsabbagh3
|
ecf81336db
|
Finished FE and BE high-level
|
2019-09-08 19:28:53 -04:00 |
|
felsabbagh3
|
981bf0afe5
|
FE Done
|
2019-09-08 18:36:47 -04:00 |
|
felsabbagh3
|
ad45758a35
|
Before Fetch->FE
|
2019-09-08 18:09:11 -04:00 |
|
felsabbagh3
|
c310e7381f
|
Icache interface
|
2019-09-08 17:36:09 -04:00 |
|
felsabbagh3
|
5e6804703f
|
Decode in FE
|
2019-09-08 17:24:51 -04:00 |
|
felsabbagh3
|
ac9b06bf7d
|
Before FE BE abstraction
|
2019-09-08 16:21:37 -04:00 |
|
felsabbagh3
|
fe09aafbb4
|
Interface Checkpoint 2 - Remove Lints
|
2019-09-05 19:32:37 -04:00 |
|
felsabbagh3
|
2d0e41db63
|
checkpoint: Added icache struct
|
2019-09-03 16:19:06 -04:00 |
|