Blaise Tine
|
369c2c625c
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
codetector
|
e901fb6a3a
|
remove async reset for FPGA synthesis
|
2020-02-19 23:19:05 -05:00 |
|
wgulian3
|
8d20b52ea2
|
Cleanup imports of VX_define
|
2020-02-04 10:57:32 -05:00 |
|
fares
|
53c78b905a
|
Switched to g++
|
2019-11-16 12:23:59 -05:00 |
|
felsabbagh3
|
7ed88ce4c1
|
Fixed AA d_cache sizing errors
|
2019-11-11 15:20:58 -05:00 |
|
felsabbagh3
|
92e88a7bb2
|
Fixed cache meta
|
2019-11-10 15:38:39 -05:00 |
|
felsabbagh3
|
31de18c328
|
Changed tb
|
2019-11-10 15:06:06 -05:00 |
|
Savan Roshan
|
e4ee2a9cbd
|
Parameterization working
|
2019-11-07 00:14:46 -05:00 |
|
Savan Roshan
|
8468e7d4d9
|
Added prefix DCACHE_
|
2019-11-05 08:33:38 -05:00 |
|
Savan Roshan
|
8264339853
|
Added Parameterization
|
2019-11-04 13:20:34 -05:00 |
|
felsabbagh3
|
7863175233
|
Set associative bank working
|
2019-10-30 14:57:20 -04:00 |
|
Lingjun Zhu
|
b6558714ca
|
Finished synthesis with all memory but no optimization
|
2019-10-28 16:18:11 -04:00 |
|
Lingjun Zhu
|
0b30b3a35f
|
Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data
|
2019-10-28 15:06:23 -04:00 |
|
felsabbagh3
|
a8d063e9ad
|
Synthesis Cleanup 1
|
2019-10-28 13:43:12 -04:00 |
|
felsabbagh3
|
715982cca7
|
Modelsim Working + Simulating + dumping - Some bugs
|
2019-10-27 03:36:02 -04:00 |
|
felsabbagh3
|
1181af1df2
|
Modelsim basic sim
|
2019-10-26 00:34:57 -04:00 |
|
felsabbagh3
|
c85c01e082
|
Parametized cache
|
2019-10-25 13:36:06 -04:00 |
|
felsabbagh3
|
89d0390965
|
CACHE FINALLY WORKING
|
2019-10-25 04:01:23 -04:00 |
|
felsabbagh3
|
1645a04b1d
|
Fixed SM + added def SYN
|
2019-10-22 15:56:30 -04:00 |
|
felsabbagh3
|
9d8273afe4
|
Finished Cache Integration
|
2019-10-22 06:02:08 -04:00 |
|