wgulian3
3b74f071a7
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df
Remove VX_define.h and *_synth and runtime/config.h
2020-03-26 04:07:17 -04:00
Blaise Tine
a7eb9a0c38
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
4626389ee2
code refactoring
2020-03-26 01:41:01 -04:00
felsabbagh3
4e6de0dc38
Fixed most of the cache issues, mat_add left
2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
wgulian3
902aa685b1
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
1c82f9a11d
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
05b7ffff12
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
felsabbagh3
65f3ced608
Fixed no L3 Verilator issues
2020-03-13 15:11:20 -07:00
felsabbagh3
fc94168e32
Removed L3 for synthesis
2020-03-13 15:01:46 -07:00
wgulian3
dd2c9cd9d7
Add power analysis Make target
2020-03-12 13:14:50 -04:00
wgulian3
b1e77bec44
replace procedural continuous assignments and force MLAB inference for generic_queue_ll
2020-03-10 17:46:48 -04:00
wgulian3
372a1ad905
minor tweaks to appease quartus
...
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
2020-03-10 12:15:30 -04:00
felsabbagh3
13c6cbfa5d
L3 and CLUSTRING WORKS
2020-03-10 02:41:47 -07:00
felsabbagh3
cf0173ae15
Fixed Stall Pipeline Logic
2020-03-09 22:08:46 -07:00
felsabbagh3
e2ffbcf14b
MULTICORE WITH L2 WORKING
2020-03-09 01:17:11 -07:00
felsabbagh3
a539630a0a
Added Vortex SOC
2020-03-08 15:24:21 -07:00
felsabbagh3
b5b04a7070
Added Shared Memory
2020-03-08 15:00:53 -07:00
felsabbagh3
b9a95631bc
Icache stage mods + removed shared memory
2020-03-08 14:04:55 -07:00
felsabbagh3
2f94b26af0
Icache working
2020-03-08 13:59:35 -07:00
felsabbagh3
507d20f413
Cache Working on Mem Copy
2020-03-08 01:55:15 -08:00
felsabbagh3
f03f3fe037
Fixed all Cache Warnings
2020-03-07 14:34:05 -08:00
Blaise Tine
3953a71180
fixed write logic in generic_queue_ll
2020-03-07 06:56:11 -05:00
felsabbagh3
9bf0add937
Made the cache module configurable for multi-instantiation
2020-03-07 00:49:40 -08:00
felsabbagh3
fb23812e95
Added Lower Level Cache Hit Queue
2020-03-06 23:04:42 -08:00
felsabbagh3
44f6c68fe9
Got queue_ll to work by modifying when to update bypass
2020-03-06 22:50:20 -08:00
Blaise Tine
0816426662
added unit_test
2020-03-06 10:31:31 -05:00
Blaise Tine
9f5235dc3d
added generic_queue_ll
2020-03-05 10:43:15 -05:00
Blaise Tine
9c56a10f15
synthesis fixes
2020-03-05 09:11:43 -05:00
Blaise Tine
33868512ac
synthesis fixes
2020-03-05 07:03:23 -05:00
Blaise Tine
66a46f81ce
synthesis fixes
2020-03-05 06:58:51 -05:00
felsabbagh3
457e8644f3
Added Snoop Invalidate/Writeback Req type
2020-03-05 01:30:16 -08:00
felsabbagh3
e0620a6f6a
Added fill_invalidator
2020-03-04 23:55:02 -08:00
felsabbagh3
b038bdb491
New Cache Design Passing All Tests
2020-03-04 23:24:32 -08:00
felsabbagh3
b0b9b8238e
Passing some cases
2020-03-04 04:05:54 -08:00
felsabbagh3
8f001ac6f2
Added All Interfaces
2020-03-03 22:48:49 -08:00
felsabbagh3
73cecd3866
Added Core Interface
2020-03-03 22:14:56 -08:00
felsabbagh3
57a96e02b1
Fixed some other timing issues
2020-03-03 21:15:44 -08:00
felsabbagh3
08986bf1dc
Fixed incorrect valid and'ing in execute
2020-03-03 20:57:20 -08:00
felsabbagh3
a47f7c11ec
Finished cache, dram imp + interfaces left
2020-03-03 19:42:33 -08:00
felsabbagh3
8ece8d8893
Fixed miss reserv to support ST->LD sequences
2020-03-03 17:04:39 -08:00
felsabbagh3
80af320fdb
Before fixing miss rsrv for ST->LD sequences
2020-03-03 16:57:05 -08:00
felsabbagh3
361fc2c3fe
Finished st0
2020-03-03 02:49:30 -08:00
felsabbagh3
3a970bbe7b
Connected cache to bank
2020-03-02 23:24:17 -08:00
felsabbagh3
fc5621cd1d
Everything except bank internals
2020-03-02 23:08:54 -08:00
felsabbagh3
abca2f7abb
Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
2020-03-01 22:27:18 -08:00
felsabbagh3
6bf25b5b78
+Added icache stage -- 3rd case of AUIPC os broken?
2020-03-01 18:01:02 -08:00
wgulian3
23aabbf01d
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
2020-02-22 20:16:13 -05:00
wgulian3
b2afe526fe
Update multiply for not SYN_FUNC
2020-02-21 23:20:04 -05:00
