wgulian3
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5b3df797a4
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Add modified RTL files for parameterized builds with VX_define_synth.v
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2020-03-20 04:04:15 -04:00 |
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wgulian3
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a931b588c2
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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24f20a2da4
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Added Vortex SOC
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2020-03-08 15:24:21 -07:00 |
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Blaise Tine
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ddafe96ca6
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fixed write logic in generic_queue_ll
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2020-03-07 06:56:11 -05:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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f6cc05eaa2
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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wgulian3
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a32d654263
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Merge branch 'master' into fpga_synthesis
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2020-02-18 03:35:12 -05:00 |
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felsabbagh3
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28ce40eebf
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fixed make w + vx_gpr_stage csr schedule
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2020-02-18 00:26:44 -08:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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b6375e76de
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:24:49 -04:00 |
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felsabbagh3
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4cae140ac1
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Mem technology compiling but still reading all zeros
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2019-10-18 16:45:42 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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6b729fd2ea
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minor
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2019-10-18 01:46:38 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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3c3a443bd5
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New RF with Evaluation
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2019-09-11 01:04:23 -04:00 |
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felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
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ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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Hyesoon Kim
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6b3b124a30
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fix typo of std=c++11
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2019-06-12 07:32:20 -04:00 |
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felsabbagh3
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9cd8ee8579
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Added std=c++11
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2019-06-11 23:21:48 -07:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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cc0fb0eece
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better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
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7a528c5ef2
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Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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felsabbagh3
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01d142c6e6
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rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
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656475b3b3
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Passing Most tests
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2019-03-21 23:47:48 -04:00 |
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felsabbagh3
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d08d389177
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Started on rtl (Finished till decode)
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2019-03-21 02:23:10 -04:00 |
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