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412 Commits 7 Branches 0 Tags
9ebf806c6d790d90529217efd4775dd8ab96e58a
Commit Graph
39 Commits
Author SHA1 Message Date
fares 19dba43849 vecadd bug fixing + ebreak for termination 2019-11-15 14:18:45 -05:00
felsabbagh3 715982cca7 Modelsim Working + Simulating + dumping - Some bugs 2019-10-27 03:36:02 -04:00
felsabbagh3 1181af1df2 Modelsim basic sim 2019-10-26 00:34:57 -04:00
felsabbagh3 31d3d51392 WSPAWN imp + tested 2019-10-21 23:35:53 -04:00
felsabbagh3 b6375e76de Readded IPDOM stack + SPLIT/Join tested 2019-10-21 21:24:49 -04:00
felsabbagh3 bab1852a99 Added Split/Join - not tested 2019-10-21 03:03:15 -04:00
felsabbagh3 84f5ccb484 Added CSR TID/WID reads 2019-10-21 02:10:05 -04:00
felsabbagh3 f7b55427b4 Added ISA2 infrastructure with bugs 2019-10-18 05:21:32 -04:00
felsabbagh3 559c64cb36 Cleanup 2019-10-18 02:20:38 -04:00
felsabbagh3 505bbc20c8 Removed FWD 2019-10-18 02:01:39 -04:00
felsabbagh3 8bc3b8b0a5 Need to link SystemC for sc_time_stamp() 2019-10-14 23:25:14 -04:00
felsabbagh3 ee83e6d8c8 Moved GPR to back-end 2019-10-14 19:08:32 -04:00
felsabbagh3 e67310acfb New Warp Scheduler + VCD Enable 2019-09-15 00:12:41 -04:00
felsabbagh3 1b25b10644 Full Evaluation Attempt 1 2019-09-11 01:39:00 -04:00
felsabbagh3 8d143d7739 Quartus + GPR evaluation 2019-09-10 20:23:01 -04:00
felsabbagh3 4e8da1811a New GPR structure - Clone or WSPAWN 2019-09-09 22:17:20 -04:00
felsabbagh3 1882147370 GPR Wrapper Interface Done 2019-09-09 14:04:07 -04:00
felsabbagh3 bce9bc443c GPR Wrapper in Decode 2019-09-09 01:03:13 -04:00
felsabbagh3 ac9b06bf7d Before FE BE abstraction 2019-09-08 16:21:37 -04:00
felsabbagh3 fe09aafbb4 Interface Checkpoint 2 - Remove Lints 2019-09-05 19:32:37 -04:00
felsabbagh3 d7afef04a9 Sim Work miss 2019-05-18 23:42:55 +04:00
felsabbagh3 48468ed26a Proper SIMT with fine-grain scheduler implemented 2019-05-10 00:49:54 -07:00
felsabbagh3 a6c13bc38c Inefficient context aware desgin 2019-05-08 15:55:06 -07:00
felsabbagh3 79356c7ab1 Changed hierarchy + Identified private + public modules 2019-05-07 23:45:05 -07:00
felsabbagh3 f21eaec79f Provisioned SM 2019-04-05 19:25:54 -04:00
felsabbagh3 8c2ae97510 1 WARP 8 THREADS TESTED + FULLY WORKING 2019-03-31 05:21:00 -04:00
felsabbagh3 c83ef94d02 1 WARP 2 THREADS WORKING 2019-03-31 05:02:55 -04:00
felsabbagh3 4aac33b298 Using verilog For-loops + Passing all tests 2019-03-30 22:55:13 -04:00
felsabbagh3 a3a3b21de7 Using verilog For-loops + Passing all tests 2019-03-30 22:09:03 -04:00
felsabbagh3 99a0792a0c Passing all tests with 2 threads 2019-03-30 03:54:20 -04:00
felsabbagh3 d02c3d25b7 sync 2019-03-27 13:52:13 -04:00
felsabbagh3 68f3ba84e5 Added HW threads - Infinite loop + fixed valid 2019-03-27 03:53:59 -04:00
felsabbagh3 9b42e79dcf Added HW threads - Infinite loop 2019-03-27 03:44:14 -04:00
felsabbagh3 cc0fb0eece better use of valid signal 2019-03-27 00:07:59 -04:00
felsabbagh3 7a528c5ef2 Packing data wires + ALU module 2019-03-26 19:17:11 -04:00
felsabbagh3 097e0217de Added support for MUL/DIV (Passes all tests) 2019-03-22 03:54:59 -04:00
felsabbagh3 01d142c6e6 rtl passing all tests 2019-03-22 02:44:53 -04:00
felsabbagh3 656475b3b3 Passing Most tests 2019-03-21 23:47:48 -04:00
felsabbagh3 d08d389177 Started on rtl (Finished till decode) 2019-03-21 02:23:10 -04:00