Blaise Tine
|
7b8fe11e6a
|
unused variables refactoring
|
2021-08-05 01:46:26 -07:00 |
|
Blaise Tine
|
79fd92a1b4
|
minor update
|
2021-07-30 17:43:15 -07:00 |
|
Blaise Tine
|
160ff94a22
|
minor update
|
2021-07-30 16:01:22 -07:00 |
|
Blaise Tine
|
3d19588e57
|
bus arbiters refactoring
|
2021-07-30 16:00:09 -07:00 |
|
Blaise Tine
|
ea1e0f201e
|
OUTPUT_REG refactoring
|
2021-07-23 06:58:37 -07:00 |
|
Blaise Tine
|
5c58f7eec6
|
minor update
|
2021-07-16 12:57:50 -07:00 |
|
Blaise Tine
|
a8f9a2559d
|
minor update
|
2021-07-15 12:25:51 -07:00 |
|
Blaise Tine
|
c5aec572b5
|
minor update
|
2021-07-15 11:46:43 -07:00 |
|
Blaise Tine
|
7d01be367c
|
reset network refactoring
|
2021-07-15 11:34:55 -07:00 |
|
Blaise Tine
|
22cf698e69
|
minor update
|
2021-07-13 05:25:44 -07:00 |
|
Blaise Tine
|
10e9ee124b
|
using onehot multiplexer to reduce critical path
|
2021-07-08 00:26:59 -07:00 |
|
Blaise Tine
|
dc34c5c5bd
|
minor update
|
2021-07-03 04:47:19 -07:00 |
|
Blaise Tine
|
93fee18d59
|
minor update
|
2021-07-01 02:59:44 -07:00 |
|
Blaise Tine
|
1ea738ed26
|
lkg build
|
2021-06-25 16:28:10 -07:00 |
|
Blaise Tine
|
a3a7239b4d
|
critical path optimizations
|
2021-06-23 01:51:23 -07:00 |
|
Blaise Tine
|
b8fd2308e1
|
arbiter specialization
|
2021-06-22 21:02:37 -07:00 |
|
Blaise Tine
|
57143f5889
|
synthesis optimizations
|
2021-06-17 16:43:43 -07:00 |
|
Blaise Tine
|
47c3234659
|
minor update
|
2021-06-13 10:58:48 -07:00 |
|
Blaise Tine
|
adf033b0aa
|
non-cacheable memory address critical paths optimizations
|
2021-06-10 12:47:18 -07:00 |
|
Blaise Tine
|
aff5903a22
|
minor ibuffer critical path optimization.
|
2021-04-19 20:53:13 -07:00 |
|
Blaise Tine
|
16bef8937b
|
adding empty to index_buffer
|
2021-03-30 10:15:42 -07:00 |
|
Blaise Tine
|
b33a994f49
|
minor update
|
2021-03-29 23:51:05 -07:00 |
|
Blaise Tine
|
bd40e7db70
|
minor update - mux reordering to reduce critical path on input data
|
2021-03-21 11:43:57 -07:00 |
|
Blaise Tine
|
062d02ddce
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2021-03-04 20:51:03 -08:00 |
|
Blaise Tine
|
3f5fd6d394
|
using shiftreg-based skid buffers
|
2021-02-28 02:20:09 -08:00 |
|
Blaise Tine
|
ebee332e9d
|
minor update
|
2021-02-27 02:31:05 -08:00 |
|
Blaise Tine
|
20d704b4d3
|
skid buffer optimization
|
2021-02-27 02:29:48 -08:00 |
|
Blaise Tine
|
700f9eea19
|
moving MUL unit into ALU unit
|
2021-02-23 13:49:02 -08:00 |
|
Blaise Tine
|
143319d557
|
minor optimization
|
2021-02-18 16:03:16 -08:00 |
|
Blaise Tine
|
073964fdf7
|
minor update
|
2021-02-12 08:52:06 -08:00 |
|
Blaise Tine
|
72b6713a72
|
updating fdiv/fsqrt bram hex files, reset_delay updaet
|
2021-02-04 09:02:18 -08:00 |
|
Blaise Tine
|
5419859281
|
fcvt fix
|
2021-01-25 02:22:00 -08:00 |
|
Blaise Tine
|
8775f63ec4
|
lkg build rollout with 16cores optimization on arria10
|
2021-01-24 16:49:22 -08:00 |
|
Blaise Tine
|
a046bd7a73
|
cache pipeline optimization
|
2021-01-17 17:19:52 -08:00 |
|
Blaise Tine
|
ed216ab39d
|
minor updates
|
2021-01-17 13:58:43 -08:00 |
|
Blaise Tine
|
d4e7b28be8
|
cache refactoring
|
2021-01-17 00:18:56 -08:00 |
|
Blaise Tine
|
ad6e0b4e77
|
sp_ram byteen fix
|
2021-01-15 16:28:03 -08:00 |
|
Blaise Tine
|
fe64c47f60
|
ccip write fix
|
2021-01-14 22:49:06 -08:00 |
|
Blaise Tine
|
b4b5d6f0ab
|
minor updates
|
2021-01-12 15:19:38 -08:00 |
|
Blaise Tine
|
ceae724207
|
minor updates
|
2021-01-12 11:24:36 -08:00 |
|
Blaise Tine
|
7e93d253f2
|
minor update
|
2021-01-10 22:03:23 -08:00 |
|
Blaise Tine
|
e770824d47
|
fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
|
2021-01-10 20:26:15 -08:00 |
|
Blaise Tine
|
06945533cf
|
fixed l2/l3 caches related bugs
|
2021-01-09 16:32:55 -08:00 |
|
Blaise Tine
|
5c83c594c1
|
minor update
|
2021-01-07 17:25:59 -08:00 |
|
Blaise Tine
|
146c285aa0
|
minor update
|
2021-01-06 19:59:04 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
39bff921be
|
cache bug fixes
|
2021-01-05 05:04:49 -08:00 |
|
Blaise Tine
|
4815ab099c
|
using single-port block ram for cache tags, restoring core reset signal
|
2021-01-02 19:53:41 -08:00 |
|
Blaise Tine
|
da9649c2a3
|
fixed pipe register reset issue in synthesis
|
2021-01-01 14:54:18 -08:00 |
|
Blaise Tine
|
36602cfa6a
|
buffering core reset signal
|
2021-01-01 11:46:30 -08:00 |
|