felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
|
1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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31d3d51392
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WSPAWN imp + tested
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2019-10-21 23:35:53 -04:00 |
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felsabbagh3
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b6375e76de
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:24:49 -04:00 |
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felsabbagh3
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bab1852a99
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Added Split/Join - not tested
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2019-10-21 03:03:15 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
|
505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
|
8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
|
1b25b10644
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Full Evaluation Attempt 1
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2019-09-11 01:39:00 -04:00 |
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felsabbagh3
|
8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
|
4e8da1811a
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New GPR structure - Clone or WSPAWN
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2019-09-09 22:17:20 -04:00 |
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felsabbagh3
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1882147370
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GPR Wrapper Interface Done
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2019-09-09 14:04:07 -04:00 |
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felsabbagh3
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bce9bc443c
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GPR Wrapper in Decode
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2019-09-09 01:03:13 -04:00 |
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felsabbagh3
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ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
|
d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
|
48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
|
a6c13bc38c
|
Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
|
79356c7ab1
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Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
|
f21eaec79f
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Provisioned SM
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2019-04-05 19:25:54 -04:00 |
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felsabbagh3
|
8c2ae97510
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1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
|
c83ef94d02
|
1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
|
4aac33b298
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Using verilog For-loops + Passing all tests
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2019-03-30 22:55:13 -04:00 |
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felsabbagh3
|
a3a3b21de7
|
Using verilog For-loops + Passing all tests
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2019-03-30 22:09:03 -04:00 |
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felsabbagh3
|
99a0792a0c
|
Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
|
d02c3d25b7
|
sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
|
68f3ba84e5
|
Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
|
9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
|
cc0fb0eece
|
better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
|
7a528c5ef2
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Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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felsabbagh3
|
097e0217de
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Added support for MUL/DIV (Passes all tests)
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2019-03-22 03:54:59 -04:00 |
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felsabbagh3
|
01d142c6e6
|
rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
|
656475b3b3
|
Passing Most tests
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2019-03-21 23:47:48 -04:00 |
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felsabbagh3
|
d08d389177
|
Started on rtl (Finished till decode)
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2019-03-21 02:23:10 -04:00 |
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