Blaise Tine
22be51b0c8
fixed multicore build
2020-03-28 01:40:26 -04:00
Blaise Tine
8bb1f66220
missing rtl changes from OPAE
2020-03-27 22:37:35 -04:00
Blaise Tine
2ed7bd3755
fixed multicore build
2020-03-27 21:04:23 -04:00
Blaise Tine
2415199a8c
minor build fixes
2020-03-27 20:56:18 -04:00
Blaise Tine
073173067f
adding back build_config target dependency
2020-03-27 12:41:03 -04:00
Blaise Tine
50829e522b
update
2020-03-26 04:19:53 -04:00
Blaise Tine
3252d52694
refactoring RTL simulator and Makefile
2020-03-26 04:14:36 -04:00
wgulian3
f126a23114
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
Blaise Tine
bf3d1fb5a2
code refactoring
2020-03-26 01:41:01 -04:00
wgulian3
10ebfd7e24
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
5b3df797a4
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
wgulian3
a931b588c2
minor tweaks to appease quartus
...
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
2020-03-10 12:15:30 -04:00
felsabbagh3
469334f23e
MULTICORE WITH L2 WORKING
2020-03-09 01:17:11 -07:00
felsabbagh3
24f20a2da4
Added Vortex SOC
2020-03-08 15:24:21 -07:00
Blaise Tine
ddafe96ca6
fixed write logic in generic_queue_ll
2020-03-07 06:56:11 -05:00
felsabbagh3
aa1a0ee376
Passing some cases
2020-03-04 04:05:54 -08:00
felsabbagh3
f6cc05eaa2
Everything except bank internals
2020-03-02 23:08:54 -08:00
wgulian3
a32d654263
Merge branch 'master' into fpga_synthesis
2020-02-18 03:35:12 -05:00
felsabbagh3
28ce40eebf
fixed make w + vx_gpr_stage csr schedule
2020-02-18 00:26:44 -08:00
wgulian3
8318aff69f
Support exec multi-cycle for div/mul
2020-02-13 13:17:46 -05:00
felsabbagh3
01efe02e8b
CACHE WORKING just needs lb/sb
2019-10-25 03:03:09 -04:00
felsabbagh3
1e648c5819
FIxed first circular issue
2019-10-24 10:38:04 -04:00
felsabbagh3
1645a04b1d
Fixed SM + added def SYN
2019-10-22 15:56:30 -04:00
felsabbagh3
9d8273afe4
Finished Cache Integration
2019-10-22 06:02:08 -04:00
felsabbagh3
b7af8c3f34
Integrated Shared Memory
2019-10-22 05:03:47 -04:00
felsabbagh3
1bfafca896
Cleanup before integration
2019-10-22 03:03:17 -04:00
felsabbagh3
b6375e76de
Readded IPDOM stack + SPLIT/Join tested
2019-10-21 21:24:49 -04:00
felsabbagh3
4cae140ac1
Mem technology compiling but still reading all zeros
2019-10-18 16:45:42 -04:00
felsabbagh3
f7d826593f
TMC working and tested
2019-10-18 16:09:06 -04:00
felsabbagh3
6b729fd2ea
minor
2019-10-18 01:46:38 -04:00
felsabbagh3
6779d0fade
Instruction Multiplex LSU/EXU 1 cycle DONE
2019-10-17 22:29:21 -04:00
felsabbagh3
95047fcadc
Rename Stage that removes the need for forwarding
2019-10-17 00:48:54 -04:00
felsabbagh3
8bc3b8b0a5
Need to link SystemC for sc_time_stamp()
2019-10-14 23:25:14 -04:00
felsabbagh3
ee83e6d8c8
Moved GPR to back-end
2019-10-14 19:08:32 -04:00
felsabbagh3
e67310acfb
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
felsabbagh3
3c3a443bd5
New RF with Evaluation
2019-09-11 01:04:23 -04:00
felsabbagh3
8d143d7739
Quartus + GPR evaluation
2019-09-10 20:23:01 -04:00
felsabbagh3
ac9b06bf7d
Before FE BE abstraction
2019-09-08 16:21:37 -04:00
felsabbagh3
fe09aafbb4
Interface Checkpoint 2 - Remove Lints
2019-09-05 19:32:37 -04:00
Hyesoon Kim
6b3b124a30
fix typo of std=c++11
2019-06-12 07:32:20 -04:00
felsabbagh3
9cd8ee8579
Added std=c++11
2019-06-11 23:21:48 -07:00
felsabbagh3
c83ef94d02
1 WARP 2 THREADS WORKING
2019-03-31 05:02:55 -04:00
felsabbagh3
cc0fb0eece
better use of valid signal
2019-03-27 00:07:59 -04:00
felsabbagh3
7a528c5ef2
Packing data wires + ALU module
2019-03-26 19:17:11 -04:00
felsabbagh3
01d142c6e6
rtl passing all tests
2019-03-22 02:44:53 -04:00
felsabbagh3
656475b3b3
Passing Most tests
2019-03-21 23:47:48 -04:00
felsabbagh3
d08d389177
Started on rtl (Finished till decode)
2019-03-21 02:23:10 -04:00
