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f53256f854
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quartus projects
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2020-04-21 12:28:37 -07:00 |
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5798cf6e15
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RTL refactoring
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2020-04-21 07:13:56 -07:00 |
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b6ce2dd3b8
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opae build fix
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2020-04-21 02:08:20 -07:00 |
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cb0afd3eec
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fix quartus build
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2020-04-21 00:55:18 -07:00 |
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d6255f0445
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-21 03:20:18 -04:00 |
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d85c0af5d6
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remove tab spaces
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2020-04-21 03:19:47 -04:00 |
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07d308d2ce
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update
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2020-04-21 02:41:37 -04:00 |
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43a8bf4326
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RTL code refactoring
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2020-04-21 01:52:12 -04:00 |
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20ae78f434
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fix simX build
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2020-04-21 01:31:32 -04:00 |
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ba4e736782
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RTL code refactoring
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2020-04-21 01:03:37 -04:00 |
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cfa8626bf7
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RTL code refactoring
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2020-04-20 23:44:30 -04:00 |
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786817d601
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opae build fix
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2020-04-20 19:53:47 -07:00 |
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d79e36912f
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fix opae build
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2020-04-20 12:51:42 -07:00 |
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3cbecfcef0
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opae build fix
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2020-04-20 12:32:01 -07:00 |
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f835fabbe3
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-20 15:07:49 -04:00 |
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b76f8696bd
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removing *.vh file for opae build
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2020-04-20 15:07:27 -04:00 |
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91207a0fcb
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opae update
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2020-04-20 12:06:47 -07:00 |
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8e7046a388
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RTL code refactoring
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2020-04-20 14:05:08 -04:00 |
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1a2823da0d
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RTL code refactoring
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2020-04-20 13:52:24 -04:00 |
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94e4f056db
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RTL code refactoring
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2020-04-20 13:10:56 -04:00 |
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a0e15af0dc
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RTL code refactoring
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2020-04-20 13:01:42 -04:00 |
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e8a4923eb4
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RTL code refactoring
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2020-04-20 12:09:30 -04:00 |
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e8072bab77
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RTL code refactoring
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2020-04-20 11:20:41 -04:00 |
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45990e391f
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RTL code refactoring
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2020-04-20 10:21:06 -04:00 |
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0c81a3ae19
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RTL code refactoring
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2020-04-20 08:01:46 -04:00 |
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62c1c3fdbb
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RTL code refactoring
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2020-04-20 07:24:20 -04:00 |
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58850a2fe8
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RTL code refactoring
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2020-04-20 06:59:13 -04:00 |
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07135263f5
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RTL code refactoring
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2020-04-20 06:47:24 -04:00 |
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5671b08a5e
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merge
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2020-04-20 06:06:54 -04:00 |
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felsabbagh3
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5e570d95d8
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Fixed two variabled driving the dram_delay signal
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2020-04-20 00:33:24 -07:00 |
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e9dfa828fe
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RTL code refactoring
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2020-04-19 09:24:04 -04:00 |
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3139d37610
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RTL code refactoring
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2020-04-19 08:45:46 -04:00 |
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164eb5454c
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RTL code refactoring
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2020-04-19 05:21:46 -04:00 |
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885869df4a
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adding DEBUG MACROS
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2020-04-19 04:59:52 -04:00 |
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9b476f1e17
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RTL code refactoring
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2020-04-19 03:38:00 -04:00 |
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460aabf6b1
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refactor interfaces
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2020-04-16 10:40:40 -04:00 |
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31f906f9fd
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fixed all build warnings
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2020-04-16 10:22:46 -04:00 |
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81745f08c9
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added config.vh
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2020-04-16 07:49:19 -04:00 |
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c913e542e9
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adding POCL Dockerfile
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2020-04-14 19:46:53 -04:00 |
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12dc4d6874
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refactoring fixes
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2020-04-14 19:39:59 -04:00 |
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22c8da7490
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renamed Vortex_SOC to Vortex_Socket
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2020-04-14 08:33:32 -04:00 |
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c132149801
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minor update
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2020-04-14 08:27:37 -04:00 |
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c88af7889c
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remove temp files
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2020-04-14 08:26:12 -04:00 |
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3bbaea1332
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project directories restructuring
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2020-04-14 08:24:49 -04:00 |
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fc155e1223
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project directories reorganization
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2020-04-14 06:35:20 -04:00 |
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1de06fd9c0
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update
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2020-04-13 07:40:51 -04:00 |
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dd1ba977c6
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update opencl benchmakr kernel compilation steps
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2020-04-13 07:37:35 -04:00 |
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97a31401f7
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rename driver dummy to stub
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2020-04-10 22:40:58 -04:00 |
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217dfb48ef
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adding README for OPAE hw
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2020-04-08 11:44:06 -04:00 |
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809b4ded5d
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-06 10:31:00 -04:00 |
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