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Add single cycle edition

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CGH0S7
2024-12-31 01:30:15 +08:00
parent de44f7d8d3
commit b4cb98d8a9
126 changed files with 1242 additions and 629 deletions
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@ -20,10 +20,6 @@ module regfile_32x32(
input R1_en, input R1_en,
R1_clk, R1_clk,
output [31:0] R1_data, output [31:0] R1_data,
input [4:0] R2_addr,
input R2_en,
R2_clk,
output [31:0] R2_data,
input [4:0] W0_addr, input [4:0] W0_addr,
input W0_en, input W0_en,
W0_clk, W0_clk,
@ -37,7 +33,6 @@ module regfile_32x32(
end // always @(posedge) end // always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 32'bx; assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 32'bx; assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
assign R2_data = R2_en ? Memory[R2_addr] : 32'bx;
endmodule endmodule
module Core( module Core(
@ -49,83 +44,73 @@ module Core(
input [31:0] io_dmem_rdata, input [31:0] io_dmem_rdata,
output io_dmem_wen, output io_dmem_wen,
output [31:0] io_dmem_wdata, output [31:0] io_dmem_wdata,
output io_exit, output io_exit
output [31:0] io_gp
); );
wire [31:0] mem_wb_data; wire [31:0] _regfile_ext_R0_data;
wire exe_jmp_flg;
wire exe_br_flg;
wire [31:0] _regfile_ext_R1_data; wire [31:0] _regfile_ext_R1_data;
wire [31:0] _regfile_ext_R2_data; reg [31:0] pc_reg;
reg [31:0] id_reg_pc; wire [31:0] _pc_plus4_T = pc_reg + 32'h4;
reg [31:0] id_reg_inst; wire [9:0] _GEN = {io_imem_inst[31:28], io_imem_inst[5:0]};
reg [31:0] exe_reg_pc; wire jmp_flg = io_imem_inst[31:28] == 4'h3 | _GEN == 10'h8;
reg [4:0] exe_reg_wb_addr; wire [31:0] rs_data = (|(io_imem_inst[25:21])) ? _regfile_ext_R1_data : 32'h0;
reg [31:0] exe_reg_op1_data; wire [31:0] rt_data = (|(io_imem_inst[20:16])) ? _regfile_ext_R0_data : 32'h0;
reg [31:0] exe_reg_op2_data; wire [11:0] _GEN_0 = {io_imem_inst[31:26], io_imem_inst[5:0]};
reg [31:0] exe_reg_rs2_data; wire _csignals_T_5 = _GEN_0 == 12'h20;
reg [4:0] exe_reg_exe_fun; wire _csignals_T_7 = io_imem_inst[31:28] == 4'h8;
reg [1:0] exe_reg_mem_wen; wire _csignals_T_9 = _GEN_0 == 12'h22;
reg [1:0] exe_reg_rf_wen; wire _csignals_T_11 = _GEN_0 == 12'h24;
reg [2:0] exe_reg_wb_sel; wire _csignals_T_13 = _GEN_0 == 12'h25;
reg [31:0] exe_reg_imm_b_sext; wire _csignals_T_15 = _GEN_0 == 12'h26;
reg [31:0] mem_reg_pc; wire _csignals_T_17 = io_imem_inst[31:28] == 4'hC;
reg [4:0] mem_reg_wb_addr; wire _csignals_T_19 = io_imem_inst[31:28] == 4'hD;
reg [31:0] mem_reg_rs2_data; wire _csignals_T_21 = _GEN_0 == 12'h2A;
reg [1:0] mem_reg_mem_wen; wire _csignals_T_23 = io_imem_inst[31:28] == 4'h4;
reg [1:0] mem_reg_rf_wen; wire _csignals_T_25 = io_imem_inst[31:28] == 4'h5;
reg [2:0] mem_reg_wb_sel; wire [16:0] _GEN_1 = {io_imem_inst[31:21], io_imem_inst[5:0]};
reg [31:0] mem_reg_alu_out; wire _csignals_T_27 = _GEN_1 == 17'h0;
reg [4:0] wb_reg_wb_addr; wire _csignals_T_29 = _GEN_1 == 17'h2;
reg [1:0] wb_reg_rf_wen; wire _csignals_T_31 = _GEN_1 == 17'h3;
reg [31:0] wb_reg_wb_data; wire _csignals_T_33 = io_imem_inst[31:28] == 4'h3;
reg [31:0] if_reg_pc; wire _csignals_T_35 = _GEN == 10'h8;
wire _id_inst_T = exe_br_flg | exe_jmp_flg; wire [4:0] csignals_0 =
wire _id_rs2_data_hazard_T = exe_reg_rf_wen == 2'h1; _csignals_T_5 | _csignals_T_7
wire stall_flg = ? 5'h1
_id_rs2_data_hazard_T & (|(id_reg_inst[25:21])) : _csignals_T_9
& id_reg_inst[25:21] == exe_reg_wb_addr | _id_rs2_data_hazard_T ? 5'h2
& (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr; : _csignals_T_11
wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h0 : id_reg_inst; ? 5'h3
wire _id_rs1_data_T = id_inst[25:21] == 5'h0; : _csignals_T_13
wire _id_rs2_data_T_2 = mem_reg_rf_wen == 2'h1; ? 5'h4
wire _id_rs1_data_T_3 = id_inst[25:21] == mem_reg_wb_addr & _id_rs2_data_T_2; : _csignals_T_15
wire _id_rs2_data_T_5 = wb_reg_rf_wen == 2'h1; ? 5'h5
wire _id_rs1_data_T_6 = id_inst[25:21] == wb_reg_wb_addr & _id_rs2_data_T_5; : _csignals_T_17
wire [31:0] id_rs2_data = ? 5'h3
id_inst[20:16] == 5'h0 : _csignals_T_19
? 32'h0 ? 5'h4
: id_inst[20:16] == mem_reg_wb_addr & _id_rs2_data_T_2 : _csignals_T_21
? mem_wb_data ? 5'h9
: id_inst[20:16] == wb_reg_wb_addr & _id_rs2_data_T_5 : _csignals_T_23
? wb_reg_wb_data ? 5'hB
: _regfile_ext_R1_data; : _csignals_T_25
wire [16:0] _GEN = {id_inst[31:26], id_inst[10:0]}; ? 5'hC
wire _csignals_T_5 = _GEN == 17'h20; : _csignals_T_27
wire _csignals_T_7 = id_inst[31:28] == 4'h8; ? 5'h6
wire _csignals_T_9 = _GEN == 17'h22; : _csignals_T_29
wire _csignals_T_11 = _GEN == 17'h24; ? 5'h7
wire _csignals_T_13 = _GEN == 17'h25; : _csignals_T_31
wire _csignals_T_15 = _GEN == 17'h26; ? 5'h8
wire _csignals_T_17 = id_inst[31:28] == 4'hC; : _csignals_T_33
wire _csignals_T_19 = id_inst[31:28] == 4'hD; ? 5'h1
wire _csignals_T_21 = _GEN == 17'h2A; : _csignals_T_35 ? 5'hD : 5'h0;
wire _csignals_T_23 = id_inst[31:28] == 4'h4; wire _GEN_2 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
wire _csignals_T_25 = id_inst[31:28] == 4'h5; wire _GEN_3 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_2;
wire _csignals_T_27 = id_inst[31:28] == 4'h3;
wire _csignals_T_29 = id_inst[31:23] == 9'h1E0;
wire _GEN_0 = _csignals_T_27 | _csignals_T_29;
wire [4:0] _csignals_T_31 = {4'h0, _GEN_0};
wire _GEN_1 = _csignals_T_5 | _csignals_T_7;
wire _GEN_2 = _csignals_T_23 | _csignals_T_25;
wire _GEN_3 = _csignals_T_21 | _GEN_2;
wire [1:0] csignals_1 = wire [1:0] csignals_1 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _GEN_3 | ~_csignals_T_33
? 2'h1 ? 2'h1
: _csignals_T_27 ? 2'h2 : {1'h0, ~_csignals_T_29}; : 2'h2;
wire [2:0] _csignals_T_70 = wire [2:0] _csignals_T_85 =
_csignals_T_5 _csignals_T_5
? 3'h1 ? 3'h1
: _csignals_T_7 : _csignals_T_7
@ -134,254 +119,140 @@ module Core(
? 3'h1 ? 3'h1
: _csignals_T_17 | _csignals_T_19 : _csignals_T_17 | _csignals_T_19
? 3'h2 ? 3'h2
: _GEN_3 ? 3'h1 : _csignals_T_27 ? 3'h4 : {_csignals_T_29, 2'h1}; : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
wire [1:0] _csignals_T_87 = {1'h0, _GEN_0}; wire _GEN_4 = _csignals_T_23 | _csignals_T_25;
wire _GEN_4 = wire _GEN_5 =
_csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13 _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
| _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21; | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
wire [2:0] _csignals_T_100 = {2'h0, _csignals_T_29}; wire [1:0] _csignals_T_136 =
wire _id_op1_data_T = csignals_1 == 2'h1; _GEN_5 ? 2'h1 : _GEN_4 ? 2'h0 : _GEN_2 ? 2'h1 : {2{_csignals_T_33}};
wire _id_op1_data_T_1 = csignals_1 == 2'h2; wire _op1_data_T = csignals_1 == 2'h1;
wire [35:0] id_op2_data = wire _op1_data_T_1 = csignals_1 == 2'h2;
_csignals_T_70 == 3'h1 wire [31:0] op1_data = _op1_data_T ? rs_data : _op1_data_T_1 ? pc_reg : 32'h0;
? {4'h0, id_rs2_data} wire [31:0] op2_data =
: _csignals_T_70 == 3'h2 _csignals_T_85 == 3'h1
? {4'h0, {16{id_inst[15]}}, id_inst[15:0]} ? rt_data
: _csignals_T_70 == 3'h3 : _csignals_T_85 == 3'h2
? {4'h0, {22{id_inst[15]}}, id_inst[15:11], id_inst[25:21]} ? {{16{io_imem_inst[15]}}, io_imem_inst[15:0]}
: _csignals_T_70 == 3'h4 : _csignals_T_85 == 3'h4 ? {4'h0, io_imem_inst[25:0], 2'h0} : 32'h0;
? {{6{id_inst[23]}}, id_inst[25:0], 4'h0} wire _alu_out_T = csignals_0 == 5'h1;
: {4'h0, _csignals_T_70 == 3'h5 ? {id_inst[15:0], 16'h0} : 32'h0}; wire [31:0] _alu_out_T_1 = op1_data + op2_data;
wire [31:0] _exe_alu_out_T_30 = exe_reg_op1_data + exe_reg_op2_data; wire _alu_out_T_3 = csignals_0 == 5'h2;
wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0]; wire [31:0] _alu_out_T_4 = op1_data - op2_data;
wire [31:0] _GEN_5 = {27'h0, exe_reg_op2_data[4:0]}; wire _alu_out_T_6 = csignals_0 == 5'h3;
wire [31:0] _exe_alu_out_T_46 = wire [31:0] _alu_out_T_7 = op1_data & op2_data;
exe_reg_exe_fun == 5'h1 wire _alu_out_T_8 = csignals_0 == 5'h4;
? _exe_alu_out_T_30 wire [31:0] _alu_out_T_9 = op1_data | op2_data;
: exe_reg_exe_fun == 5'h2 wire _alu_out_T_10 = csignals_0 == 5'h5;
? exe_reg_op1_data - exe_reg_op2_data wire [31:0] _alu_out_T_11 = op1_data ^ op2_data;
: exe_reg_exe_fun == 5'h3 wire _alu_out_T_12 = csignals_0 == 5'h6;
? exe_reg_op1_data & exe_reg_op2_data wire [62:0] _alu_out_T_14 = {31'h0, op1_data} << op2_data[4:0];
: exe_reg_exe_fun == 5'h4 wire _alu_out_T_16 = csignals_0 == 5'h7;
? exe_reg_op1_data | exe_reg_op2_data wire [31:0] _GEN_6 = {27'h0, op2_data[4:0]};
: exe_reg_exe_fun == 5'h5 wire [31:0] _alu_out_T_18 = op1_data >> _GEN_6;
? exe_reg_op1_data ^ exe_reg_op2_data wire _alu_out_T_19 = csignals_0 == 5'h8;
: exe_reg_exe_fun == 5'h6 wire [31:0] _alu_out_T_22 = $signed($signed(op1_data) >>> _GEN_6);
? _exe_alu_out_T_14[31:0] wire _alu_out_T_24 = csignals_0 == 5'h9;
: exe_reg_exe_fun == 5'h7 wire _alu_out_T_28 = csignals_0 == 5'hD;
? exe_reg_op1_data >> _GEN_5 wire [31:0] _GEN_7 = {31'h0, $signed(op1_data) < $signed(op2_data)};
: exe_reg_exe_fun == 5'h8 wire [31:0] alu_out =
? $signed($signed(exe_reg_op1_data) >>> _GEN_5) _alu_out_T
: exe_reg_exe_fun == 5'h9 ? _alu_out_T_1
? {31'h0, : _alu_out_T_3
$signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)} ? _alu_out_T_4
: exe_reg_exe_fun == 5'hA : _alu_out_T_6
? {31'h0, exe_reg_op1_data < exe_reg_op2_data} ? _alu_out_T_7
: exe_reg_exe_fun == 5'h11 : _alu_out_T_8
? _exe_alu_out_T_30 & 32'hFFFFFFFE ? _alu_out_T_9
: exe_reg_exe_fun == 5'h12 : _alu_out_T_10
? exe_reg_op1_data ? _alu_out_T_11
: 32'h0; : _alu_out_T_12
wire _exe_br_flg_T_3 = exe_reg_op1_data == exe_reg_op2_data; ? _alu_out_T_14[31:0]
assign exe_br_flg = : _alu_out_T_16
exe_reg_exe_fun == 5'hB ? _alu_out_T_18
? _exe_br_flg_T_3 : _alu_out_T_19
: exe_reg_exe_fun == 5'hC & ~_exe_br_flg_T_3; ? _alu_out_T_22
assign exe_jmp_flg = exe_reg_wb_sel == 3'h3; : _alu_out_T_24
assign mem_wb_data = ? _GEN_7
mem_reg_wb_sel == 3'h2 : _alu_out_T_28 ? op1_data : 32'h0;
? io_dmem_rdata wire _br_flg_T_3 = op1_data == op2_data;
: mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out; wire br_flg =
csignals_0 == 5'hB ? _br_flg_T_3 : csignals_0 == 5'hC & ~_br_flg_T_3;
wire [31:0] br_target = {{14{io_imem_inst[15]}}, io_imem_inst[15:0], 2'h0} + pc_reg;
wire [31:0] wb_data =
_csignals_T_136 == 2'h2 ? io_dmem_rdata : (&_csignals_T_136) ? _pc_plus4_T : alu_out;
`ifndef SYNTHESIS `ifndef SYNTHESIS
always @(posedge clock) begin always @(posedge clock) begin
if ((`PRINTF_COND_) & ~reset) begin if ((`PRINTF_COND_) & ~reset) begin
automatic logic [31:0] id_rs1_data = $fwrite(32'h80000002, "---------------\n");
_id_rs1_data_T $fwrite(32'h80000002, "io.pc: 0x%x\ninst: 0x%x \n", pc_reg, io_imem_inst);
? 32'h0 $fwrite(32'h80000002, "pc_next: 0x%x\n",
: _id_rs1_data_T_3 br_flg ? br_target : jmp_flg ? alu_out : _pc_plus4_T);
? mem_wb_data $fwrite(32'h80000002, "rs_addr: 0x%x\n", io_imem_inst[25:21]);
: _id_rs1_data_T_6 ? wb_reg_wb_data : _regfile_ext_R2_data; $fwrite(32'h80000002, "rd_addr: 0x%x\n", io_imem_inst[15:11]);
$fwrite(32'h80000002, "---------------------\n"); $fwrite(32'h80000002, "rs_data: 0x%x\n", rs_data);
$fwrite(32'h80000002, "id_reg_pc: 0x%x\n", id_reg_pc); $fwrite(32'h80000002, "wb_data: 0x%x\n", wb_data);
$fwrite(32'h80000002, "id_reg_inst: 0x%x\n", id_reg_inst); $fwrite(32'h80000002, "---------------\n");
$fwrite(32'h80000002, "id_inst: 0x%x\n", id_inst);
$fwrite(32'h80000002, "id_rs1_addr: 0x%x\n", id_inst[25:21]);
$fwrite(32'h80000002, "id_rs2_addr: 0x%x\n", id_inst[20:16]);
$fwrite(32'h80000002, "id_wb_addr: 0x%x\n", id_inst[15:11]);
$fwrite(32'h80000002, "id_exe_fun: 0x%x\n",
_GEN_1
? 5'h1
: _csignals_T_9
? 5'h2
: _csignals_T_11
? 5'h3
: _csignals_T_13
? 5'h4
: _csignals_T_15
? 5'h5
: _csignals_T_17
? 5'h3
: _csignals_T_19
? 5'h4
: _csignals_T_21
? 5'h9
: _csignals_T_23
? 5'hB
: _csignals_T_25
? 5'hC
: _csignals_T_31);
$fwrite(32'h80000002, "id_op1_sel: 0x%x\n", csignals_1);
$fwrite(32'h80000002, "id_op1_data: 0x%x\n",
_id_op1_data_T ? id_rs1_data : _id_op1_data_T_1 ? id_reg_pc : 32'h0);
$fwrite(32'h80000002, "id_op2_sel: 0x%x\n", _csignals_T_70);
$fwrite(32'h80000002, "id_op2_data: 0x%x\n", id_op2_data);
$fwrite(32'h80000002, "id_mem_wen: 0x%x\n", 2'h0);
$fwrite(32'h80000002, "id_rf_wen: 0x%x\n",
_GEN_4 ? 2'h1 : _GEN_2 ? 2'h0 : _csignals_T_87);
$fwrite(32'h80000002, "id_wb_sel: 0x%x\n",
_GEN_4 ? 3'h1 : _GEN_2 ? 3'h0 : _csignals_T_27 ? 3'h3 : _csignals_T_100);
$fwrite(32'h80000002, "id_rs1_data: 0x%x\n", id_rs1_data);
$fwrite(32'h80000002, "id_rs2_data: 0x%x\n", id_rs2_data);
$fwrite(32'h80000002, "exe_alu_out: 0x%x\n", _exe_alu_out_T_46);
$fwrite(32'h80000002, "mem_reg_pc: 0x%x\n", mem_reg_pc);
$fwrite(32'h80000002, "mem_reg_alu_out: 0x%x\n", mem_reg_alu_out);
$fwrite(32'h80000002, "mem_wb_data: 0x%x\n", mem_wb_data);
$fwrite(32'h80000002, "wb_reg_wb_data: 0%x\n", wb_reg_wb_data);
$fwrite(32'h80000002, "---------------------\n");
end end
end // always @(posedge) end // always @(posedge)
`endif // not def SYNTHESIS `endif // not def SYNTHESIS
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin if (reset)
id_reg_pc <= 32'h0; pc_reg <= 32'h0;
id_reg_inst <= 32'h0; else if (br_flg)
exe_reg_pc <= 32'h0; pc_reg <= br_target;
exe_reg_wb_addr <= 5'h0; else if (jmp_flg) begin
exe_reg_op1_data <= 32'h0; if (_alu_out_T)
exe_reg_op2_data <= 32'h0; pc_reg <= _alu_out_T_1;
exe_reg_rs2_data <= 32'h0; else if (_alu_out_T_3)
exe_reg_exe_fun <= 5'h0; pc_reg <= _alu_out_T_4;
exe_reg_mem_wen <= 2'h0; else if (_alu_out_T_6)
exe_reg_rf_wen <= 2'h0; pc_reg <= _alu_out_T_7;
exe_reg_wb_sel <= 3'h0; else if (_alu_out_T_8)
exe_reg_imm_b_sext <= 32'h0; pc_reg <= _alu_out_T_9;
mem_reg_pc <= 32'h0; else if (_alu_out_T_10)
mem_reg_wb_addr <= 5'h0; pc_reg <= _alu_out_T_11;
mem_reg_rs2_data <= 32'h0; else if (_alu_out_T_12)
mem_reg_mem_wen <= 2'h0; pc_reg <= _alu_out_T_14[31:0];
mem_reg_rf_wen <= 2'h0; else if (_alu_out_T_16)
mem_reg_wb_sel <= 3'h0; pc_reg <= _alu_out_T_18;
mem_reg_alu_out <= 32'h0; else if (_alu_out_T_19)
wb_reg_wb_addr <= 5'h0; pc_reg <= _alu_out_T_22;
wb_reg_rf_wen <= 2'h0; else if (_alu_out_T_24)
wb_reg_wb_data <= 32'h0; pc_reg <= _GEN_7;
if_reg_pc <= 32'h400000; else if (_alu_out_T_28) begin
end if (_op1_data_T)
else begin pc_reg <= rs_data;
if (~stall_flg) else if (~_op1_data_T_1)
id_reg_pc <= if_reg_pc; pc_reg <= 32'h0;
if (_id_inst_T)
id_reg_inst <= 32'h0;
else if (~stall_flg)
id_reg_inst <= io_imem_inst;
exe_reg_pc <= id_reg_pc;
exe_reg_wb_addr <= id_inst[15:11];
if (_id_op1_data_T) begin
if (_id_rs1_data_T)
exe_reg_op1_data <= 32'h0;
else if (_id_rs1_data_T_3)
exe_reg_op1_data <= mem_wb_data;
else if (_id_rs1_data_T_6)
exe_reg_op1_data <= wb_reg_wb_data;
else
exe_reg_op1_data <= _regfile_ext_R2_data;
end end
else if (_id_op1_data_T_1)
exe_reg_op1_data <= id_reg_pc;
else else
exe_reg_op1_data <= 32'h0; pc_reg <= 32'h0;
exe_reg_op2_data <= id_op2_data[31:0];
exe_reg_rs2_data <= id_rs2_data;
if (_GEN_1)
exe_reg_exe_fun <= 5'h1;
else if (_csignals_T_9)
exe_reg_exe_fun <= 5'h2;
else if (_csignals_T_11)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_13)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_15)
exe_reg_exe_fun <= 5'h5;
else if (_csignals_T_17)
exe_reg_exe_fun <= 5'h3;
else if (_csignals_T_19)
exe_reg_exe_fun <= 5'h4;
else if (_csignals_T_21)
exe_reg_exe_fun <= 5'h9;
else if (_csignals_T_23)
exe_reg_exe_fun <= 5'hB;
else if (_csignals_T_25)
exe_reg_exe_fun <= 5'hC;
else
exe_reg_exe_fun <= _csignals_T_31;
exe_reg_mem_wen <= 2'h0;
if (_GEN_4) begin
exe_reg_rf_wen <= 2'h1;
exe_reg_wb_sel <= 3'h1;
end
else if (_GEN_2) begin
exe_reg_rf_wen <= 2'h0;
exe_reg_wb_sel <= 3'h0;
end
else begin
exe_reg_rf_wen <= _csignals_T_87;
if (_csignals_T_27)
exe_reg_wb_sel <= 3'h3;
else
exe_reg_wb_sel <= _csignals_T_100;
end
exe_reg_imm_b_sext <= {{14{id_inst[15]}}, id_inst[15:0], 2'h0};
mem_reg_pc <= exe_reg_pc;
mem_reg_wb_addr <= exe_reg_wb_addr;
mem_reg_rs2_data <= exe_reg_rs2_data;
mem_reg_mem_wen <= exe_reg_mem_wen;
mem_reg_rf_wen <= exe_reg_rf_wen;
mem_reg_wb_sel <= exe_reg_wb_sel;
mem_reg_alu_out <= _exe_alu_out_T_46;
wb_reg_wb_addr <= mem_reg_wb_addr;
wb_reg_rf_wen <= mem_reg_rf_wen;
wb_reg_wb_data <= mem_wb_data;
if (exe_br_flg)
if_reg_pc <= exe_reg_pc + exe_reg_imm_b_sext;
else if (exe_jmp_flg)
if_reg_pc <= _exe_alu_out_T_46;
else if (~stall_flg)
if_reg_pc <= if_reg_pc + 32'h4;
end end
else
pc_reg <= _pc_plus4_T;
end // always @(posedge) end // always @(posedge)
regfile_32x32 regfile_ext ( regfile_32x32 regfile_ext (
.R0_addr (5'h3), .R0_addr (io_imem_inst[20:16]),
.R0_en (1'h1), .R0_en (1'h1),
.R0_clk (clock), .R0_clk (clock),
.R0_data (io_gp), .R0_data (_regfile_ext_R0_data),
.R1_addr (id_inst[20:16]), .R1_addr (io_imem_inst[25:21]),
.R1_en (1'h1), .R1_en (1'h1),
.R1_clk (clock), .R1_clk (clock),
.R1_data (_regfile_ext_R1_data), .R1_data (_regfile_ext_R1_data),
.R2_addr (id_inst[25:21]), .W0_addr (io_imem_inst[15:11]),
.R2_en (1'h1), .W0_en
.R2_clk (clock), (_GEN_5 | ~_GEN_4
.R2_data (_regfile_ext_R2_data), & (_csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33)),
.W0_addr (wb_reg_wb_addr),
.W0_en (_id_rs2_data_T_5),
.W0_clk (clock), .W0_clk (clock),
.W0_data (wb_reg_wb_data) .W0_data (wb_data)
); );
assign io_imem_addr = if_reg_pc; assign io_imem_addr = pc_reg;
assign io_dmem_addr = mem_reg_alu_out; assign io_dmem_addr = alu_out;
assign io_dmem_wen = mem_reg_mem_wen[0]; assign io_dmem_wen = 1'h0;
assign io_dmem_wdata = mem_reg_rs2_data; assign io_dmem_wdata = rt_data;
assign io_exit = id_reg_inst == 32'h114514; assign io_exit = io_imem_inst == 32'h114514;
endmodule endmodule
// VCS coverage exclude_file // VCS coverage exclude_file
@ -449,7 +320,7 @@ module mem_4096x8(
end // always @(posedge) end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ `ifdef ENABLE_INITIAL_MEM_
initial initial
$readmemh("src/hex/mem.hex", Memory); $readmemh("src/hex/addi.hex", Memory);
`endif // ENABLE_INITIAL_MEM_ `endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 8'bx; assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
@ -539,10 +410,9 @@ module Memory(
endmodule endmodule
module TopOrigin( module TopOrigin(
input clock, input clock,
reset, reset,
output io_exit, output io_exit
output [31:0] io_gp
); );
wire [31:0] _memory_io_imem_inst; wire [31:0] _memory_io_imem_inst;
@ -560,8 +430,7 @@ module TopOrigin(
.io_dmem_rdata (_memory_io_dmem_rdata), .io_dmem_rdata (_memory_io_dmem_rdata),
.io_dmem_wen (_core_io_dmem_wen), .io_dmem_wen (_core_io_dmem_wen),
.io_dmem_wdata (_core_io_dmem_wdata), .io_dmem_wdata (_core_io_dmem_wdata),
.io_exit (io_exit), .io_exit (io_exit)
.io_gp (io_gp)
); );
Memory memory ( Memory memory (
.clock (clock), .clock (clock),

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{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":3342},"type":"LinePosition"}}

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[debug] not up to date. inChanged = true, force = false
[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...
[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")

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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

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[debug] [zinc] IncrementalCompile -----------
[debug] IncrementalCompile.incrementalCompile
[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries
[debug] current source = Set()
[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
[debug] Full compilation, no sources in previous analysis.

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[debug] About to delete class files:
[debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

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[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...
[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")

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[debug] [zinc] IncrementalCompile -----------
[debug] IncrementalCompile.incrementalCompile
[debug] previous = Stamps for: 0 products, 0 sources, 0 libraries
[debug] current source = Set()
[debug] > initialChanges = InitialChanges(Changes(added = Set(), removed = Set(), changed = Set(), unmodified = ...),Set(),Set(),API Changes: Set())
[debug] Full compilation, no sources in previous analysis.

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[debug] About to delete class files:
[debug] We backup class files:
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[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] About to delete class files: [debug] About to delete class files:
[debug] We backup class files: [debug] We backup class files:
[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak
[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/target/scala-2.12/sbt-1.0/classes.bak [debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/target/scala-2.12/sbt-1.0/classes.bak

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