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Merge remote-tracking branch 'origin/main' into bringup2

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This commit is contained in:
Jerry Zhao
2023-02-28 16:19:14 -08:00
parent 2a4c5e6f88 be27029707
commit 66e4448008
70 changed files with 5729 additions and 4799 deletions
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5
.github/scripts/check-commit.sh vendored
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@@ -98,11 +98,6 @@ dir="sims"
branches=("master" "main" "dev" "1.13.x")
search
submodules=("hammer")
dir="vlsi"
branches=("master")
search
submodules=("fpga-shells")
dir="fpga"
branches=("main")

25
.github/scripts/defaults.sh vendored
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@@ -23,11 +23,16 @@ LOCAL_CHIPYARD_DIR=$GITHUB_WORKSPACE
LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator
LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
# CI uses temp directories with very long names
# explicitly force socket creation to use /tmp to avoid name length errors
# https://github.com/sbt/sbt/pull/6887
JAVA_TMP_DIR=$(mktemp -d -t ci-cy-XXXXXXXX)
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif chipyard-nocores"
grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip constellation"
@@ -37,32 +42,26 @@ grouping["group-fpga"]="arty vcu118 vc707"
declare -A mapping
mapping["chipyard-rocket"]=""
mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeConfig"
mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeFastUARTConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-fftgenerator"]=" CONFIG=FFTRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
mapping["constellation"]=" SUB_PROJECT=constellation"

2
.github/scripts/remote-do-rtl-build.sh vendored
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@@ -53,5 +53,5 @@ read -a keys <<< ${grouping[$1]}
for key in "${keys[@]}"
do
export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" ${mapping[$key]}
make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_TMP_DIR=$JAVA_TMP_DIR SBT_OPTS="$REMOTE_SBT_OPTS" ${mapping[$key]}
done

3
.github/scripts/remote-run-firesim-scala-tests.sh vendored
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@@ -16,4 +16,5 @@ cd $REMOTE_CHIPYARD_DIR
# Run Firesim Scala Tests
export FIRESIM_ENV_SOURCED=1;
export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]}
JAVA_TOOL_OPTIONS="$REMOTE_JAVA_OPTS -Djava.io.tmpdir=$(mktemp -d -t cy-fsim-XXXXXXXX)"
make -C $REMOTE_FIRESIM_DIR JAVA_TOOL_OPTIONS="$JAVA_TOOL_OPTIONS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]}

43
.github/scripts/run-tests.sh vendored
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@@ -35,9 +35,6 @@ case $1 in
chipyard-dmirocket)
run_bmark ${mapping[$1]}
;;
chipyard-lbwif)
run_bmark ${mapping[$1]}
;;
chipyard-boom)
run_bmark ${mapping[$1]}
;;
@@ -69,21 +66,33 @@ case $1 in
(cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
;;
chipyard-streaming-passthrough)
make -C $LOCAL_CHIPYARD_DIR/tests
chipyard-manymmioaccels)
make -C $LOCAL_CHIPYARD_DIR/tests
# test streaming-passthrough
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
;;
chipyard-streaming-fir)
make -C $LOCAL_CHIPYARD_DIR/tests
# test streaming-fir
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
;;
chipyard-spiflashread)
# test nvdla
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary-fast
# test fft
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
;;
chipyard-manyperipherals)
# SPI Flash read tests, then bmark tests
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary-fast
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv run-binary-fast
run_bmark ${mapping[$1]}
;;
chipyard-spiflashwrite)
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary-fast
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv run-binary-fast
[[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
;;
tracegen)
@@ -101,16 +110,8 @@ case $1 in
chipyard-sodor)
run_asm ${mapping[$1]}
;;
chipyard-nvdla)
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary-fast
;;
chipyard-fftgenerator)
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
;;
chipyard-constellation)
run_bmark ${mapping[$1]}
make run-binary-hex BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
icenet)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}

1
.github/workflows/chipyard-full-flow.yml vendored
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@@ -13,6 +13,7 @@ defaults:
env:
REMOTE_WORK_DIR: ${{ secrets.BUILDDIR }}/cy-ci-shared/cy-${{ github.sha }}
JAVA_TMP_DIR: /tmp/cy-${{ github.sha }}-full
jobs:
cancel-prior-workflows:

141
.github/workflows/chipyard-run-tests.yml vendored
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@@ -320,7 +320,6 @@ jobs:
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-accels"
toolchain: "esp-tools"
prepare-chipyard-tracegen:
name: prepare-chipyard-tracegen
@@ -552,29 +551,6 @@ jobs:
group-key: "group-cores"
project-key: "chipyard-spike"
chipyard-fftgenerator-run-tests:
name: chipyard-fftgenerator-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-fftgenerator"
chipyard-dmirocket-run-tests:
name: chipyard-dmirocket-run-tests
needs: prepare-chipyard-peripherals
@@ -621,31 +597,8 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-spiflashwrite"
chipyard-spiflashread-run-tests:
name: chipyard-spiflashread-run-tests
needs: prepare-chipyard-peripherals
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-spiflashread"
chipyard-lbwif-run-tests:
name: chipyard-lbwif-run-tests
chipyard-manyperipherals-run-tests:
name: chipyard-manyperipherals-run-tests
needs: prepare-chipyard-peripherals
runs-on: self-hosted
steps:
@@ -665,7 +618,7 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-lbwif"
project-key: "chipyard-manyperipherals"
chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
@@ -689,77 +642,6 @@ jobs:
with:
group-key: "group-accels"
project-key: "chipyard-sha3"
toolchain: "esp-tools"
chipyard-streaming-fir-run-tests:
name: chipyard-streaming-fir-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-streaming-fir"
chipyard-streaming-passthrough-run-tests:
name: chipyard-streaming-passthrough-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-streaming-passthrough"
chipyard-hwacha-run-tests:
name: chipyard-hwacha-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-hwacha"
toolchain: "esp-tools"
chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
@@ -783,10 +665,9 @@ jobs:
with:
group-key: "group-accels"
project-key: "chipyard-gemmini"
toolchain: "esp-tools"
chipyard-nvdla-run-tests:
name: chipyard-nvdla-run-tests
chipyard-manymmioaccels-run-tests:
name: chipyard-manymmioaccels-run-tests
needs: prepare-chipyard-accels
runs-on: self-hosted
steps:
@@ -806,7 +687,7 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-nvdla"
project-key: "chipyard-manymmioaccels"
chipyard-mempress-run-tests:
name: chipyard-mempress-run-tests
@@ -830,7 +711,6 @@ jobs:
with:
group-key: "group-accels"
project-key: "chipyard-mempress"
toolchain: "esp-tools"
tracegen-boom-run-tests:
@@ -1036,16 +916,11 @@ jobs:
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-dmirocket-run-tests,
chipyard-fftgenerator-run-tests,
chipyard-spiflashread-run-tests,
chipyard-spiflashwrite-run-tests,
chipyard-lbwif-run-tests,
chipyard-manyperipherals-run-tests,
chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests,
chipyard-streaming-passthrough-run-tests,
chipyard-hwacha-run-tests,
chipyard-gemmini-run-tests,
chipyard-nvdla-run-tests,
chipyard-manymmioaccels-run-tests,
chipyard-mempress-run-tests,
chipyard-constellation-run-tests,
tracegen-boom-run-tests,

3
.gitmodules vendored
View File

@@ -28,9 +28,6 @@
[submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "vlsi/hammer"]
path = vlsi/hammer
url = https://github.com/ucb-bar/hammer.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git

2
.pre-commit-config.yaml
View File

@@ -2,7 +2,7 @@
# See https://pre-commit.com/hooks.html for more hooks
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v3.2.0
rev: v4.4.0
hooks:
- id: trailing-whitespace
- id: end-of-file-fixer

9
build.sbt
View File

@@ -12,7 +12,10 @@ lazy val commonSettings = Seq(
assembly / assemblyMergeStrategy := { _ match {
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
case _ => MergeStrategy.first}},
scalacOptions ++= Seq("-deprecation","-unchecked"),
scalacOptions ++= Seq(
"-deprecation",
"-unchecked",
"-Ymacro-annotations"), // fix hierarchy API
unmanagedBase := (chipyardRoot / unmanagedBase).value,
allDependencies := {
// drop specific maven dependencies in subprojects in favor of Chipyard's version
@@ -170,7 +173,7 @@ lazy val tracegen = (project in file("generators/tracegen"))
.settings(commonSettings)
lazy val icenet = (project in file("generators/icenet"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -206,7 +209,7 @@ lazy val sha3 = (project in file("generators/sha3"))
.settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(chiselTestSettings)
.settings(commonSettings)

38
common.mk
View File

@@ -17,7 +17,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog) \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"
@@ -91,7 +91,7 @@ endif
#########################################################################################
# copy over bootrom files
#########################################################################################
$(build_dir) $(OUT_DIR):
$(build_dir):
mkdir -p $@
$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
@@ -101,7 +101,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
# create firrtl file rule and variables
#########################################################################################
# AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \
@@ -144,7 +144,8 @@ SFC_MFC_TARGETS = \
$(MFC_MODEL_HRCHY_JSON) \
$(MFC_MODEL_SMEMS_JSON) \
$(MFC_FILELIST) \
$(MFC_BB_MODS_FILELIST)
$(MFC_BB_MODS_FILELIST) \
$(GEN_COLLATERAL_DIR)
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
@@ -161,6 +162,7 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
# hence we remove them manually by using jq before passing them to firtool
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
rm -rf $(GEN_COLLATERAL_DIR)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
@@ -172,16 +174,18 @@ endif
--no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \
--output-annotation-file $(SFC_ANNO_FILE) \
--target-dir $(OUT_DIR) \
--target-dir $(GEN_COLLATERAL_DIR) \
--input-file $(FIRRTL_FILE) \
--annotation-file $(FINAL_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
-DX $(SFC_LEVEL) \
-X $(SFC_LEVEL) \
$(EXTRA_FIRRTL_OPTIONS))
$(EXTRA_FIRRTL_OPTIONS)) # -X and -DX are duplicates to allow for extra FIRRTL passes to be run
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
@if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
firtool \
--format=fir \
--dedup \
@@ -192,13 +196,13 @@ endif
--disable-annotation-classless \
--disable-annotation-unknown \
--mlir-timing \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--repl-seq-mem-circuit=$(MODEL) \
--annotation-file=$(SFC_ANNO_FILE) \
--split-verilog \
-o $(OUT_DIR) \
-o $(GEN_COLLATERAL_DIR) \
$(SFC_FIRRTL_FILE)
-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF)
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
@@ -211,13 +215,21 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
--out-dut-filelist $(TOP_MODS_FILELIST) \
--out-model-filelist $(MODEL_MODS_FILELIST) \
--in-all-filelist $(MFC_FILELIST) \
--target-dir $(OUT_DIR)
$(SED) -e 's;^;$(OUT_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST)
--target-dir $(GEN_COLLATERAL_DIR)
$(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST)
$(SED) -i 's/\.\///' $(TOP_MODS_FILELIST)
$(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST)
$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST)
$(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) &: $(BB_MODS_FILELIST) $(MFC_TOP_HRCHY_JSON) $(FINAL_ANNO_FILE)
$(base_dir)/scripts/split-bb-files.py \
--in-bb-f $(BB_MODS_FILELIST) \
--in-top-hrchy-json $(MFC_TOP_HRCHY_JSON) \
--in-anno-json $(FINAL_ANNO_FILE) \
--out-top-bb-f $(TOP_BB_MODS_FILELIST) \
--out-model-bb-f $(MODEL_BB_MODS_FILELIST)
$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON)
$(base_dir)/scripts/split-mems-conf.py \
--in-smems-conf $(MFC_SMEMS_CONF) \
@@ -238,8 +250,10 @@ $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE
########################################################################################
# remove duplicate files and headers in list of simulation file inputs
# note: {MODEL,TOP}_BB_MODS_FILELIST is added as a req. so that the files get generated,
# however it is really unneeded since ALL_MODS_FILELIST includes all BB files
########################################################################################
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE)
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) $(TOP_BB_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST)
sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
echo "$(TOP_SMEMS_FILE)" >> $@
echo "$(MODEL_SMEMS_FILE)" >> $@

7
conda-reqs/chipyard.yaml
View File

@@ -29,10 +29,10 @@ dependencies:
- binutils
- dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
- firtool>=1.25 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
- firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
# firemarshal deps
- python>=3.8
- python>=3.9
- bc
- patch
- which
@@ -91,6 +91,7 @@ dependencies:
- wget
- sed
- autoconf
- pre-commit
# clang-format for driver coding style enforcement.
- clang-format
@@ -121,12 +122,14 @@ dependencies:
- boto3-stubs==1.21.6
- botocore-stubs==1.24.7
- mypy-boto3-s3==1.21.0
- sty==1.0.0
- pip
- pip:
- fab-classic==1.19.1
- mypy-boto3-ec2==1.21.9
- sure==2.0.0
- pylddwrap==1.2.1
- hammer-vlsi[asap7]==1.0.1
# doc requirements
- sphinx

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4324
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134
conda-requirements-riscv-tools.yaml
View File

@@ -1,134 +0,0 @@
channels:
- ucb-bar
- conda-forge
- nodefaults
dependencies:
# https://conda-forge.org/feedstock-outputs/
# filterable list of all conda-forge packages
# https://conda-forge.org/#contribute
# instructions on adding a recipe
# https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
# documentation on package_spec syntax for constraining versions
# handy tool for introspecting package relationships and file ownership
# see https://github.com/rvalieris/conda-tree
- conda-tree
# bundle FireSim driver with deps into installer shell-script
- constructor
- gcc
- gxx
- sysroot_linux-64>=2.17 # needed to match pre-built CI XRT glibc version
- conda-gcc-specs
- binutils
- dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
- riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
- firtool # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
# firemarshal deps
- python>=3.8
- bc
- patch
- which
- diffutils
- bash
- gzip
- bzip2
- perl
- tar
- file
- findutils
- rsync
- psutil
- doit=0.35.0
- gitpython
- humanfriendly
- e2fsprogs
- ctags
- bison
- flex
- expat
- make
- pyyaml
- unzip
- readline
- coreutils
- lzop
- qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock
- jq
- bash-completion
- sbt
- ca-certificates
- mosh
- gmp
- mpfr
- mpc
- zlib
- vim
- git
- openjdk
- gengetopt
- libffi
- expat
- libusb1
- ncurses
- cmake
- graphviz
- expect
- dtc
- verilator==4.226
- screen
- elfutils
- libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
- conda-lock>=1
- wget
- sed
- autoconf
# clang-format for driver coding style enforcement.
- clang-format
- clang-tools
# python packages
# While it is possible to install using pip after creating the
# conda environment, pip's dependency resolution can conflict with
# conda and create broken environments. It's best to use the conda
# packages so that the environment is consistent
- boto3==1.20.21
- colorama==0.4.3
- argcomplete==1.12.3
- python-graphviz==0.19
- pyparsing==3.0.6
- numpy==1.19.5
- kiwisolver==1.3.1
- matplotlib-base==3.3.4
- pandas==1.1.5
- awscli==1.22.21
- pytest==6.2.5
- pytest-dependency==0.5.1
- pytest-mock==3.7.0
- moto==3.1.0
- pyyaml==5.4.1
- mypy==0.931
- types-pyyaml==6.0.4
- boto3-stubs==1.21.6
- botocore-stubs==1.24.7
- mypy-boto3-s3==1.21.0
- pip
- pip:
- fab-classic==1.19.1
- mypy-boto3-ec2==1.21.9
- sure==2.0.0
- pylddwrap==1.2.1
# doc requirements
- sphinx
- pygments
- sphinx-autobuild
- sphinx_rtd_theme
- docutils

4
docs/Chipyard-Basics/Initial-Repo-Setup.rst
View File

@@ -49,6 +49,8 @@ This is done by the following:
conda install -n base conda-lock
conda activate base
.. Note:: We also recommended switching to `libmamba <https://www.anaconda.com/blog/a-faster-conda-for-a-growing-community>`__ for much faster dependency solving.
Setting up the Chipyard Repo
-------------------------------------------
@@ -103,6 +105,8 @@ This file activates the conda environment created in ``build-setup.sh`` and sets
Once the script is run, the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables will be set properly for the toolchain requested.
You can source this file in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment:
.. Note:: If you are on a Mac or a RHEL/CentOS-based Linux distribution, you must deactivate the base conda environment with ``conda deactivate`` first before proceeding. You may also choose to keep it deactivated by default with ``conda config --set auto_activate_base false``. See this `issue <https://github.com/conda/conda/issues/9392>`__ for more details.
.. code-block:: shell
source ./env.sh

2
docs/Customization/DMA-Devices.rst
View File

@@ -20,7 +20,7 @@ that writes zeros to the memory at a configured address.
:start-after: DOC include start: DigitalTop
:end-before: DOC include end: DigitalTop
We use ``TLHelper.makeClientNode`` to create a TileLink client node for us.
We use ``TLClientNode`` to create a TileLink client node for us.
We then connect the client node to the memory system through the front bus (fbus).
For more info on creating TileLink client nodes, take a look at :ref:`TileLink-Diplomacy-Reference/NodeTypes:Client Node`.

9
docs/TileLink-Diplomacy-Reference/NodeTypes.rst
View File

@@ -16,8 +16,7 @@ on the C channel, and send grant acknowledgements on the E channel.
The L1 caches and DMA devices in RocketChip/Chipyard have client nodes.
You can add a TileLink client node to your LazyModule using the TLHelper
object from testchipip like so:
You can add a TileLink client node to your LazyModule like so:
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
:language: scala
@@ -48,8 +47,7 @@ generators optimize the hardware by not arbitrating the client to managers with
address ranges that don't overlap with its visibility.
Inside your lazy module implementation, you can call ``node.out`` to get a
list of bundle/edge pairs. If you used the TLHelper, you only specified a
single client edge, so this list will only have one pair.
list of bundle/edge pairs.
The ``tl`` bundle is a Chisel hardware bundle that connects to the IO of this
module. It contains two (in the case of TL-UL and TL-UH) or five (in the case
@@ -65,8 +63,7 @@ Manager Node
------------
TileLink managers take requests from clients on the A channel and send
responses back on the D channel. You can create a manager node using the
TLHelper like so:
responses back on the D channel. You can create a manager like so:
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
:language: scala

27
docs/VLSI/ASAP7-Tutorial.rst
View File

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi``
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``example-asap7.yml``, ``example-tools.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-sky130.yml``, ``example-tech.yml``
@@ -38,9 +38,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
* ``hammer-<vendor>-plugins``
* Core, tool, tech repositories.
* Tool plugin repositories.
* ``view_gds.py``
@@ -49,31 +49,22 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
Prerequisites
-------------
* Python 3.4+
* numpy and `gdstk <https://github.com/heitzmann/gdstk>`__ or `gdspy <https://github.com/heitzmann/gdspy>`__ packages. Note: gdspy must be version 1.4.
* Python 3.9+
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* For ASAP7 specifically (`README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ for more details):
* For ASAP7 specifically (`README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__ for more details):
* First, download the `ASAP7 v1p7 PDK <https://github.com/The-OpenROAD-Project/asap7>`__ (we recommend shallow-cloning or downloading an archive of the repository). Then, download the `encrypted Calibre decks tarball <http://asap.asu.edu/asap/>`__ tarball to a directory of choice (e.g. the root directory of the PDK) but do not extract it like the instructions say. The tech plugin is configured to extract the tarball into a cache directory for you.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision.
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh asap7
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Building the Design
--------------------
@@ -139,7 +130,7 @@ To run DRC & LVS, and view the results in Calibre:
make lvs CONFIG=TinyRocketConfig
./build/lvs-rundir/generated-scripts/view-lvs
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__.
Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors.
Simulation

44
docs/VLSI/Advanced-Usage.rst
View File

@@ -3,6 +3,14 @@
Advanced Usage
==============
Hammer Development
------------------
If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
.. code-block:: shell
pip install -e <path/to/hammer>
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
@@ -39,40 +47,54 @@ For more information about all the options that can be passed to the Hammer comm
Manual Step Execution & Dependency Tracking
-------------------------------------------
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--stop_after_step``, ``--start_before_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command.
Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
Say you need to update some power straps settings in ``new_power_straps.yml`` and want to try out the new settings:
.. code-block:: shell
make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
make redo-par HAMMER_REDO_ARGS='-p new_power_straps.yml --only_step power_straps'
The command that is executed will be:
.. code-block:: shell
./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json -p new_power_straps.yml --only_step power_straps --obj_dir /path/to/build par
Hierarchical RTL/Gate-level Simulation, Power Estimation
--------------------------------------------------------
With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, rtl-level/post-syn power estimation with Joules and post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
* ``sim-rtl``: RTL-level simulation
* ``sim-rtl-debug``: Also write a VPD waveform
* ``sim-rtl-debug``: Also write a FSDB waveform
* ``sim-syn``: Post-synthesis gate-level simulation
* ``sim-syn-debug``: Also write a VPD waveform
* ``sim-syn-timing-debug``: Timing-annotated with VPD waveform
* ``sim-syn-debug``: Also write a FSDB waveform
* ``sim-syn-timing-debug``: Timing-annotated with FSDB waveform
* ``sim-par``: Post-par gate-level simulation
* ``sim-par-debug``: Also write a VPD waveform
* ``sim-par-timing-debug``: Timing-annotated with VPD waveform
* ``sim-par-debug``: Also write a FSDB waveform
* ``sim-par-timing-debug``: Timing-annotated with FSDB waveform
* ``power-rtl``: RTL-level power estimation
* Note: this will run ``sim-rtl-debug`` first
* ``power-syn``: Post-synthesis power estimation
* Note: this will run ``sim-syn-debug`` first
* ``power-par``: Post-par power estimation
* Note: this will run ``sim-par`` first
* Note: this will run ``sim-par-debug`` first
* ``redo-`` can be appended to all above targets to break dependency tracking, like described above.
* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow. Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow (remember to override this variable). Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
The simulation configuration (e.g. binaries) can be edited for your design. See the ``Makefile`` and refer to Hammer's documentation for how to set up simulation parameters for your design.

34
docs/VLSI/Basic-Flow.rst
View File

@@ -7,32 +7,26 @@ Using Hammer To Place and Route a Custom Block
Initialize the Hammer Plug-ins
----------------------------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, depending on if you are using a technology plugin included with Hammer (ASAP7, Sky130) or as a separate plugin, you will run either of the commands below.
For Hammer-provided plugins (``<tech-plugin-name>`` is ``asap7`` or ``sky130``):
.. code-block:: shell
./scripts/init-vlsi.sh <tech-plugin-name>
This will pull the Hammer & CAD tool plugin submodules, assuming the technology plugins are available on github.
Currently only the asap7 technology plugin is available on github.
If you have additional private technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), you can clone them directly
into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin``.
For separate technology plugins (this is a typical use-case for proprietry process technologies with require NDAs and secure servers), submodule them directly
into VLSI directory with the name ``hammer-<tech-plugin-name>-plugin`` before calling the ``init-vlsi.sh`` script.
For example, for an imaginary process technology called tsmintel3:
.. code-block:: shell
cd vlsi
git clone git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git
Next, we define the Hammer environment into the shell:
.. code-block:: shell
cd vlsi # (if you haven't done so yet)
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
git submodule add git@my-secure-server.berkeley.edu:tsmintel3/hammer-tsmintel3-plugin.git
cd -
./scripts/init-vlsi.sh tsmintel3
If submoduled plugins need to be updated, call the ``upgrade-vlsi.sh`` script. This will checkout and pull the latest master branch.
.. Note:: Some VLSI EDA tools are supported only on RHEL-based operating systems. We recommend using Chipyard on RHEL7 and above. However, many VLSI server still have old operating systems such as RHEL6, which have software packages older than the basic chipyard requirements. In order to build Chipyard on RHEL6, you will likely need to use tool packages such as devtoolset (for example, devtoolset-8) and/or build from source gcc, git, gmake, make, dtc, cc, bison, libexpat and liby.
@@ -42,8 +36,7 @@ Setting up the Hammer Configuration Files
The first configuration file that needs to be set up is the Hammer environment configuration file ``env.yml``. In this file you need to set the paths to the EDA tools and license servers you will be using. You do not have to fill all the fields in this configuration file, you only need to fill in the paths for the tools that you will be using.
If you are working within a shared server farm environment with an LSF cluster setup (for example, the Berkeley Wireless Research Center), please note the additional possible environment configuration listed in the :ref:`VLSI/Basic-Flow:Advanced Environment Setup` segment of this documentation page.
Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the ASAP7 tutorial :ref:`tutorial` and the ``sky130``
OpenRoad example), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design.
Hammer relies on YAML-based configuration files. While these configuration can be consolidated within a single files (as is the case in the :ref:`tutorial` and the :ref:`sky130-openroad-tutorial`), the generally suggested way to work with an arbitrary process technology or tools plugins would be to use three configuration files, matching the three Hammer concerns - tools, tech, and design.
The ``vlsi`` directory includes three such example configuration files matching the three concerns: ``example-tools.yml``, ``example-tech.yml``, and ``example-design.yml``.
The ``example-tools.yml`` file configures which EDA tools hammer will use. This example file uses Cadence Innovus, Genus and Voltus, Synopsys VCS, and Mentor Calibre (which are likely the tools you will use if you're working in the Berkeley Wireless Research Center). Note that tool versions are highly sensitive to the process-technology in-use. Hence, tool versions that work with one process technology may not work with another.
@@ -52,7 +45,7 @@ The ``example-design.yml`` file contains basic build system information (how man
Finally, the ``example-tech.yml`` file is a template file for a process technology plugin configuration. We will copy this file, and replace its fields with the appropriate process technology details for the tech plugin that we have access to. For example, for the ``asap7`` tech plugin, we will replace the <tech_name> field with "asap7" and the path to the process technology files installation directory. The technology plugin (which for ASAP7 is within Hammer) will define the technology node and other parameters.
We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs (e.g. create tech-tsmintel3.yml from example-tech.yml)
We recommend copying these example configuration files and customizing them with a different name, so you can have different configuration files for different process technologies and designs (e.g. create ``tech-tsmintel3.yml`` from ``example-tech.yml``)
Building the Design
@@ -302,8 +295,11 @@ For example, if we choose to specifiy the previously mentioned ``GemminiRocketCo
bottom: 0
In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the heirarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hiearchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the hierarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hierarchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
For more information about the Hammer hierarchical flow and specifying the hierarchy and constraints, visit the `Hammer documentation <https://hammer-vlsi.readthedocs.io/en/stable/Hammer-Use/Hierarchical.html>`__.
.. Note:: You must generate the hierarchical hierarchy BEFORE running the ``make buildfile`` target. This is because Hammer encodes its hierarchical flow graph in a generated Makefile in ``$(OBJ_DIR)/hammer.d``. If you modify your physical hierarchy, you must wipe and regenerate this Makefile. Finally, you must always override the ``VLSI_TOP`` variable to be the hierarchical block that you are working on. This is required for hierarchical simulation and power flows.
.. Specifying a Custom Floorplan
.. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

3
docs/VLSI/Building-A-Chip.rst
View File

@@ -49,4 +49,5 @@ Running the VLSI tool flow
--------------------------
For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.
For setup and instructions for a VLSI tool flow in the context of Chipyard, see :ref:`hammer_basic_flow`.
For specific examples, see :ref:`tutorial`, :ref:`sky130-commercial-tutorial`, and :ref:`sky130-openroad-tutorial`.

15
docs/VLSI/Hammer.rst
View File

@@ -6,7 +6,7 @@ Core Hammer
`Hammer <https://github.com/ucb-bar/hammer>`__ is a physical design flow which encourages reusability by partitioning physical design specifications into three distinct concerns: design, CAD tool, and process technology. Hammer wraps around vendor specific technologies and tools to provide a single API to address ASIC design concerns.
Hammer allows for reusability in ASIC design while still providing the designers leeway to make their own modifications.
For more information, read the `Hammer paper <https://people.eecs.berkeley.edu/~edwardw/pubs/hammer-woset-2018.pdf>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
For more information, read the `Hammer paper <https://dl.acm.org/doi/abs/10.1145/3489517.3530672>`__ and see the `GitHub repository <https://github.com/ucb-bar/hammer>`__ and associated documentation.
Hammer implements a VLSI flow using the following high-level constructs:
@@ -30,7 +30,7 @@ VLSI Flow Control
-----------------
Sometimes we want more fine-grained control of the VLSI flow than at the action level.
The Hammer flow supports being able to start/stop before/after any of the steps in a particular action.
See the `Hammer documentation on Flow Control <https://docs.hammer-eda.org/en/latest/Hammer-Use/Flow-Control.html>`__ for a full list and description of the options.
See the `Hammer documentation on Flow Control <https://hammer-vlsi.readthedocs.io/en/latest/Hammer-Use/Flow-Control.html>`__ for a full list and description of the options.
The ``Makefile`` in the ``vlsi`` directory passes this extra information via the ``HAMMER_EXTRA_ARGS`` variable.
This variable can also be used to specify additional YAML configurations that may have
changed or been omitted from the inital build.
@@ -41,7 +41,7 @@ Configuration (Hammer IR)
To configure a Hammer flow, supply a set ``yaml`` or ``json`` configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/defaults.yml>`__.
The current set of all available Hammer APIs is codified `here <https://github.com/ucb-bar/hammer/blob/master/hammer/config/defaults.yml>`__.
Tool Plugins
============
@@ -60,10 +60,9 @@ The types of tools (by Hammer names) supported currently include:
Several configuration variables are needed to configure your tool plugin of choice.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the name of your tool, e.g. ``vlsi.core.par_tool: "innovus"``.
First, select which tool to use for each action by setting ``vlsi.core.<tool_type>_tool`` to the package name of your tool, e.g. ``vlsi.core.par_tool: "hammer.par.innovus"``.
Then, point Hammer to the folder that contains your tool plugin by setting ``vlsi.core.<tool_type>_tool_path``.
This directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
This package directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``<tool_type>.<tool_name>.version`` to a tool specific string.
The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tool.
This class should be a subclass of ``Hammer<tool_type>Tool``, which will be a subclass of ``HammerTool``. The class should implement methods for all the tool's steps.
@@ -75,10 +74,10 @@ Technology Plugins
Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``<tech_name>.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions.
The `ASAP7 plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/asap7>`__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions.
Several configuration variables are needed to configure your technology of choice.
First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``.
First, choose the technology package, e.g. ``vlsi.core.technology: hammer.technology.asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir``.
Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user.

29
docs/VLSI/Sky130-Commercial-Tutorial.rst
View File

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment.
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi-sky130``
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* ``example-sky130.yml``, ``example-tools.yml``, ``example-designs/sky130-commercial.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
@@ -38,35 +38,26 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
* ``hammer-<vendor>-plugins``
* Core, tool, tech repositories.
* Tool plugin repositories.
Prerequisites
-------------
* Python 3.6+
* numpy package
* Python 3.9+
* Genus, Innovus, Voltus, VCS, and Calibre licenses
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130
to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
Building the Design
--------------------
@@ -103,7 +94,7 @@ example-sky130.yml
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.sky130A/sky130_nda/openram_lib`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
for details about the PDK setup.
example-tools.yml
@@ -143,7 +134,7 @@ To run DRC & LVS, and view the results in Calibre:
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
For this reason, the ``example-vlsi-sky130`` script black-boxes the SRAMs for DRC/LVS analysis.
Simulation

40
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
View File

@@ -18,13 +18,17 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
* ``env.yml``
* A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
* ``example-vlsi-sky130``
* Entry point to Hammer. Contains example placeholders for hooks.
* ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml``
* Hammer IR for this tutorial.
* Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
* ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
@@ -34,15 +38,14 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>``, ``hammer/src/hammer-vlsi/technology/<tech>``
* ``hammer-<vendor>-plugins``
* Core repository, and open-source tool and technology plugins.
* Tool plugin repositories not used for this tutorial (they are provided in the hammer-vlsi package).
Prerequisites
-------------
* Python 3.6+
* numpy package
* Python 3.9+
* OpenROAD flow tools:
* Yosys (synthesis), install `from source <https://yosyshq.net/yosys/download.html>`__ or `using conda <https://anaconda.org/TimVideos/yosys>`__
@@ -50,27 +53,19 @@ Prerequisites
* Magic (DRC), install `from source <http://www.opencircuitdesign.com/magic/install.html>`__
* NetGen (LVS), install `from source <http://www.opencircuitdesign.com/netgen/install.html>`__ or `using conda <https://anaconda.org/conda-forge/netgen>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
* Sky130 PDK, install using `these directions <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
Initial Setup
-------------
In the Chipyard root, run:
In the Chipyard root, ensure that you have the Chipyard conda environment activated. Then, run:
.. code-block:: shell
./scripts/init-vlsi.sh sky130 openroad
to pull the Hammer submodule. Note that for technologies other than ``sky130`` or ``asap7``, the tech plugin submodule is cloned into the ``vlsi`` folder,
to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule is cloned in the ``vlsi`` folder,
and for the commercial tool flow (set up by omitting the ``openroad`` argument), the tool plugin submodules are cloned into the ``vlsi`` folder.
Pull the Hammer environment into the shell:
.. code-block:: shell
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
Building the Design
--------------------
To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
@@ -92,6 +87,7 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
* ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity.
* ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
* ``ENABLE_CUSTOM_FIRRTL_PASS = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog.
Running the VLSI Flow
---------------------
@@ -106,7 +102,7 @@ example-sky130.yml
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set ``technology.sky130.<sky130A, openram_lib>`` to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__
for details about the PDK setup.
@@ -163,7 +159,7 @@ To run DRC & LVS:
make lvs tutorial=sky130-openroad
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.
VLSI Flow Control
@@ -180,11 +176,11 @@ Firt, refer to the :ref:`VLSI/Hammer:VLSI Flow Control` documentation. The below
# example of re-running only floorplanning to test out a new floorplan configuration
make redo-par HAMMER_EXTRA_ARGS="--only_step floorplan_design -p example-sky130.yml"
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
See the `OpenROAD tool plugin <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__ for the full list of OpenROAD tool steps and their implementations.
Documentation
-------------
For more information about Hammer's underlying implementation, visit the `Hammer documentation website <https://docs.hammer-eda.org/en/latest/index.html>`__.
For more information about Hammer's underlying implementation, visit the `Hammer documentation website <https://hammer-vlsi.readthedocs.io/en/latest/index.html>`__.
For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/par/openroad>`__
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/sky130>`__.
For details about the plugins used in this tutorial, check out the `OpenROAD tool plugin repo + README <https://github.com/ucb-bar/hammer/blob/master/hammer/par/openroad>`__
and `Sky130 tech plugin repo + README <https://github.com/ucb-bar/hammer/blob/master/hammer/technology/sky130>`__.

12
fpga/Makefile
View File

@@ -103,17 +103,15 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl
#########################################################################################
# setup misc. sim files
#########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR)
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
-cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
touch $@
$(foreach file,\
$^,\
$(SIM_FILE_REQS),\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables

2
generators/boom

Submodule generators/boom updated: 615f4ef60f...deae9f7046

258
generators/chipyard/src/main/resources/csrc/cospike.cc Normal file
View File

@@ -0,0 +1,258 @@
#include <vector>
#include <string>
#include <riscv/sim.h>
#include <vpi_user.h>
#include <svdpi.h>
#include <sstream>
#include <set>
#define CLINT_BASE (0x2000000)
#define CLINT_SIZE (0x1000)
typedef struct system_info_t {
std::string isa;
int pmpregions;
uint64_t mem0_base;
uint64_t mem0_size;
int nharts;
std::vector<char> bootrom;
};
system_info_t* info = NULL;
sim_t* sim = NULL;
reg_t tohost_addr = 0;
reg_t fromhost_addr = 0;
std::set<reg_t> magic_addrs;
cfg_t* cfg;
static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
{
std::vector<std::pair<reg_t, mem_t*>> mems;
mems.reserve(layout.size());
for (const auto &cfg : layout) {
mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
}
return mems;
}
extern "C" void cospike_set_sysinfo(char* isa, int pmpregions,
long long int mem0_base, long long int mem0_size,
int nharts,
char* bootrom
) {
if (!info) {
info = new system_info_t;
info->isa = std::string(isa);
info->pmpregions = pmpregions;
info->mem0_base = mem0_base;
info->mem0_size = mem0_size;
info->nharts = nharts;
std::stringstream ss(bootrom);
std::string s;
while (ss >> s) {
info->bootrom.push_back(std::stoi(s));
}
}
}
extern "C" void cospike_cosim(long long int cycle,
long long int hartid,
int has_wdata,
int valid,
long long int iaddr,
unsigned long int insn,
int raise_exception,
int raise_interrupt,
unsigned long long int cause,
unsigned long long int wdata)
{
assert(info);
if (!sim) {
printf("Configuring spike cosim\n");
std::vector<mem_cfg_t> mem_cfg;
std::vector<int> hartids;
mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
for (int i = 0; i < info->nharts; i++)
hartids.push_back(i);
cfg = new cfg_t(std::make_pair(0, 0),
nullptr,
info->isa.c_str(),
"MSU",
"vlen:128,elen:64",
false,
endianness_little,
info->pmpregions,
mem_cfg,
hartids,
false,
0
);
std::vector<std::pair<reg_t, mem_t*>> mems = make_mems(cfg->mem_layout());
rom_device_t *boot_rom = new rom_device_t(info->bootrom);
mem_t *boot_addr_reg = new mem_t(0x1000);
uint64_t default_boot_addr = 0x80000000;
boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr));
// Don't actually build a clint
mem_t* clint_mem = new mem_t(CLINT_SIZE);
std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices;
// The device map is hardcoded here for now
plugin_devices.push_back(std::pair(0x4000, boot_addr_reg));
plugin_devices.push_back(std::pair(0x10000, boot_rom));
plugin_devices.push_back(std::pair(CLINT_BASE, clint_mem));
s_vpi_vlog_info vinfo;
if (!vpi_get_vlog_info(&vinfo))
abort();
std::vector<std::string> htif_args;
bool in_permissive = false;
bool cospike_debug = false;
for (int i = 1; i < vinfo.argc; i++) {
std::string arg(vinfo.argv[i]);
if (arg == "+permissive") {
in_permissive = true;
} else if (arg == "+permissive-off") {
in_permissive = false;
} else if (arg == "+cospike_debug") {
cospike_debug = true;
} else if (!in_permissive) {
htif_args.push_back(arg);
}
}
debug_module_config_t dm_config = {
.progbufsize = 2,
.max_sba_data_width = 0,
.require_authentication = false,
.abstract_rti = 0,
.support_hasel = true,
.support_abstract_csr_access = true,
.support_abstract_fpr_access = true,
.support_haltgroups = true,
.support_impebreak = true
};
printf("%s\n", info->isa.c_str());
for (int i = 0; i < htif_args.size(); i++) {
printf("%s\n", htif_args[i].c_str());
}
sim = new sim_t(cfg, false,
mems,
plugin_devices,
htif_args,
dm_config,
nullptr,
false,
nullptr,
false,
nullptr
);
sim->configure_log(true, true);
// Use our own reset vector
for (int i = 0; i < info->nharts; i++) {
sim->get_core(hartid)->get_state()->pc = 0x10040;
}
sim->set_debug(cospike_debug);
printf("Setting up htif for spike cosim\n");
((htif_t*)sim)->start();
printf("Spike cosim started\n");
tohost_addr = ((htif_t*)sim)->get_tohost_addr();
fromhost_addr = ((htif_t*)sim)->get_fromhost_addr();
printf("Tohost : %lx\n", tohost_addr);
printf("Fromhost: %lx\n", fromhost_addr);
}
processor_t* p = sim->get_core(hartid);
state_t* s = p->get_state();
uint64_t s_pc = s->pc;
if (raise_interrupt) {
printf("%d interrupt %lx\n", cycle, cause);
uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
if (interrupt_cause == 3) {
s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
} else {
printf("Unknown interrupt %lx\n", interrupt_cause);
}
}
if (raise_exception)
printf("%d exception %lx\n", cycle, cause);
if (valid) {
printf("%d Cosim: %lx", cycle, iaddr);
if (has_wdata) {
printf(" %lx", wdata);
}
printf("\n");
}
if (valid || raise_interrupt || raise_exception)
p->step(1);
if (valid) {
if (s_pc != iaddr) {
printf("%d PC mismatch %lx != %lx\n", cycle, s_pc, iaddr);
exit(1);
}
// Try to remember magic_mem addrs, and ignore these in the future
auto& mem_write = s->log_mem_write;
if (!mem_write.empty() && tohost_addr && std::get<0>(mem_write[0]) == tohost_addr) {
reg_t wdata = std::get<1>(mem_write[0]);
if (wdata >= info->mem0_base && wdata < (info->mem0_base + info->mem0_size)) {
printf("Probable magic mem %x\n", wdata);
magic_addrs.insert(wdata);
}
}
if (has_wdata) {
auto& log = s->log_reg_write;
auto& mem_read = s->log_mem_read;
reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]);
for (auto regwrite : log) {
int rd = regwrite.first >> 4;
int type = regwrite.first & 0xf;
// 0 => int
// 1 => fp
// 2 => vec
// 3 => vec hint
// 4 => csr
if ((rd != 0 && type == 0) || type == 1) {
// Override reads from some CSRs
uint64_t csr_addr = (insn >> 20) & 0xfff;
bool csr_read = (insn & 0x7f) == 0x73;
if (csr_read) printf("CSR read %lx\n", csr_addr);
if (csr_read && (
(csr_addr == 0x301) || // misa
(csr_addr == 0xf13) || // mimpid
(csr_addr == 0xf12) || // marchid
(csr_addr == 0xf11) || // mvendorid
(csr_addr == 0xb00) || // mcycle
(csr_addr == 0xb02) || // minstret
(csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
)) {
printf("CSR override\n");
s->XPR.write(rd, wdata);
} else if (!mem_read.empty() && ((magic_addrs.count(mem_read_addr) ||
(tohost_addr && mem_read_addr == tohost_addr) ||
(fromhost_addr && mem_read_addr == fromhost_addr) ||
(CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE))
))) {
// Don't check reads from tohost, reads from magic memory, or reads from clint
// Technically this could be buggy because log_mem_read only reports vaddrs, but
// no software ever should access tohost/fromhost/clint with vaddrs anyways
printf("Read override %lx\n", mem_read_addr);
s->XPR.write(rd, wdata);
} else if (wdata != regwrite.second.v[0]) {
printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, regwrite.second.v[0], wdata);
exit(1);
}
}
}
}
}
}
// }

74
generators/chipyard/src/main/resources/vsrc/cospike.v Normal file
View File

@@ -0,0 +1,74 @@
import "DPI-C" function void cospike_set_sysinfo(
input string isa,
input int pmpregions,
input longint mem0_base,
input longint mem0_size,
input int nharts,
input string bootrom
);
import "DPI-C" function void cospike_cosim(input longint cycle,
input longint hartid,
input bit has_wdata,
input bit valid,
input longint iaddr,
input int insn,
input bit raise_exception,
input bit raise_interrupt,
input longint cause,
input longint wdata
);
module SpikeCosim #(
parameter ISA,
parameter PMPREGIONS,
parameter MEM0_BASE,
parameter MEM0_SIZE,
parameter NHARTS,
parameter BOOTROM) (
input clock,
input reset,
input [63:0] cycle,
input [63:0] hartid,
input trace_0_valid,
input [63:0] trace_0_iaddr,
input [31:0] trace_0_insn,
input trace_0_exception,
input trace_0_interrupt,
input [63:0] trace_0_cause,
input trace_0_has_wdata,
input [63:0] trace_0_wdata,
input trace_1_valid,
input [63:0] trace_1_iaddr,
input [31:0] trace_1_insn,
input trace_1_exception,
input trace_1_interrupt,
input [63:0] trace_1_cause,
input trace_1_has_wdata,
input [63:0] trace_1_wdata
);
initial begin
cospike_set_sysinfo(ISA, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
end;
always @(posedge clock) begin
if (!reset) begin
if (trace_0_valid || trace_0_exception || trace_0_cause) begin
cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
trace_0_wdata);
end
if (trace_1_valid || trace_1_exception || trace_1_cause) begin
cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr,
trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause,
trace_1_wdata);
end
end
end
endmodule; // CospikeCosim

88
generators/chipyard/src/main/scala/Cospike.scala Normal file
View File

@@ -0,0 +1,88 @@
package chipyard
import chisel3._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.util._
import freechips.rocketchip.config.{Parameters, Field, Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import testchipip.TileTraceIO
case class SpikeCosimConfig(
isa: String,
pmpregions: Int,
mem0_base: BigInt,
mem0_size: BigInt,
nharts: Int,
bootrom: String
)
class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
"ISA" -> StringParam(cfg.isa),
"PMPREGIONS" -> IntParam(cfg.pmpregions),
"MEM0_BASE" -> IntParam(cfg.mem0_base),
"MEM0_SIZE" -> IntParam(cfg.mem0_size),
"NHARTS" -> IntParam(cfg.nharts),
"BOOTROM" -> StringParam(cfg.bootrom)
)) with HasBlackBoxResource
{
addResource("/csrc/cospike.cc")
addResource("/vsrc/cospike.v")
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val cycle = Input(UInt(64.W))
val hartid = Input(UInt(64.W))
val trace = Input(Vec(2, new Bundle {
val valid = Bool()
val iaddr = UInt(64.W)
val insn = UInt(32.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(64.W)
val has_wdata = Bool()
val wdata = UInt(64.W)
}))
})
}
object SpikeCosim
{
def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = {
val cosim = Module(new SpikeCosim(cfg))
val cycle = withClockAndReset(trace.clock, trace.reset) {
val r = RegInit(0.U(64.W))
r := r + 1.U
r
}
cosim.io.clock := trace.clock
cosim.io.reset := trace.reset
require(trace.numInsns <= 2)
cosim.io.cycle := cycle
cosim.io.trace.map(t => {
t.valid := false.B
t.iaddr := 0.U
t.insn := 0.U
t.exception := false.B
t.interrupt := false.B
t.cause := 0.U
})
cosim.io.hartid := hartid.U
for (i <- 0 until trace.numInsns) {
cosim.io.trace(i).valid := trace.insns(i).valid
val signed = Wire(SInt(64.W))
signed := trace.insns(i).iaddr.asSInt
cosim.io.trace(i).iaddr := signed.asUInt
cosim.io.trace(i).insn := trace.insns(i).insn
cosim.io.trace(i).exception := trace.insns(i).exception
cosim.io.trace(i).interrupt := trace.insns(i).interrupt
cosim.io.trace(i).cause := trace.insns(i).cause
cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B
cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U)
}
}
}

20
generators/chipyard/src/main/scala/HarnessBinders.scala
View File

@@ -21,7 +21,7 @@ import barstools.iocell.chisel._
import testchipip._
import chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey}
import chipyard._
import chipyard.clocking.{HasChipyardPRCI}
import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq}
@@ -354,6 +354,24 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({
}
})
class WithCospike extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.tiles
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
)
ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) }
}
})
class WithCustomBootPinPlusArg extends OverrideHarnessBinder({
(system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {
val pin = PlusArg("custom_boot_pin", width=1)

37
generators/chipyard/src/main/scala/SpikeTile.scala
View File

@@ -16,7 +16,6 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.prci.ClockSinkParameters
case class SpikeCoreParams(
val maxInsnsPerCycle: Int = 10000
) extends CoreParams {
val useVM = true
val useHypervisor = false
@@ -305,23 +304,29 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
spike.io.msip := int_bundle.msip
spike.io.meip := int_bundle.meip
spike.io.seip := int_bundle.seip.get
spike.io.ipc := outer.spikeTileParams.core.maxInsnsPerCycle.U
spike.io.ipc := PlusArg("spike-ipc", 10000, width=64)
val blockBits = log2Ceil(p(CacheBlockBytes))
spike.io.icache.a.ready := icache_tl.a.ready
icache_tl.a.valid := spike.io.icache.a.valid
icache_tl.a.bits := icacheEdge.Get(
val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true))
spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U
icache_tl.a <> icache_a_q.io.deq
icache_a_q.io.enq.valid := spike.io.icache.a.valid
icache_a_q.io.enq.bits := icacheEdge.Get(
fromSource = spike.io.icache.a.sourceid,
toAddress = (spike.io.icache.a.address >> blockBits) << blockBits,
lgSize = blockBits.U)._2
icache_tl.d.ready := true.B
spike.io.icache.d.valid := icache_tl.d.valid
spike.io.icache.d.sourceid := icache_tl.d.bits.source
spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W)))
spike.io.dcache.a.ready := dcache_tl.a.ready
dcache_tl.a.valid := spike.io.dcache.a.valid
dcache_tl.a.bits := dcacheEdge.AcquireBlock(
val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true))
spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U
dcache_tl.a <> dcache_a_q.io.deq
dcache_a_q.io.enq.valid := spike.io.dcache.a.valid
dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock(
fromSource = spike.io.dcache.a.sourceid,
toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits,
lgSize = blockBits.U,
@@ -333,9 +338,11 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
spike.io.dcache.b.source := dcache_tl.b.bits.source
spike.io.dcache.b.param := dcache_tl.b.bits.param
spike.io.dcache.c.ready := dcache_tl.c.ready
dcache_tl.c.valid := spike.io.dcache.c.valid
dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary,
val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true))
spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U
dcache_tl.c <> dcache_c_q.io.deq
dcache_c_q.io.enq.valid := spike.io.dcache.c.valid
dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary,
dcacheEdge.Release(
fromSource = spike.io.dcache.c.sourceid,
toAddress = spike.io.dcache.c.address,
@@ -369,10 +376,12 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
dcache_tl.e.valid := dcache_tl.d.valid && should_finish
dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits)
spike.io.mmio.a.ready := mmio_tl.a.ready
mmio_tl.a.valid := spike.io.mmio.a.valid
val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true))
spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U
mmio_tl.a <> mmio_a_q.io.deq
mmio_a_q.io.enq.valid := spike.io.mmio.a.valid
val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U })
mmio_tl.a.bits := Mux(spike.io.mmio.a.store,
mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store,
mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2,
mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2)

1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
View File

@@ -52,6 +52,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)

6
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -47,3 +47,9 @@ class DromajoBoomConfig extends Config(
new boom.common.WithNSmallBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MediumBoomCosimConfig extends Config(
new chipyard.harness.WithCospike ++ // attach spike-cosim
new chipyard.config.WithTraceIO ++ // enable the traceio
new boom.common.WithNMediumBooms(1) ++
new chipyard.config.AbstractConfig)

8
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
View File

@@ -56,3 +56,11 @@ class LargeNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class ManyMMIOAcceleratorRocketConfig extends Config(
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

12
generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
View File

@@ -63,3 +63,15 @@ class dmiRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: DmiRocket
class ManyPeripheralsRocketConfig extends Config(
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
View File

@@ -9,7 +9,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
import boom.common.{BoomTileAttachParams}
import cva6.{CVA6TileAttachParams}
import testchipip._
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -79,3 +78,4 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
))
}
})

6
generators/chipyard/src/main/scala/example/InitZero.scala
View File

@@ -5,14 +5,14 @@ import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import testchipip.TLHelper
import freechips.rocketchip.tilelink._
case class InitZeroConfig(base: BigInt, size: BigInt)
case object InitZeroKey extends Field[Option[InitZeroConfig]](None)
class InitZero(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode(
name = "init-zero", sourceId = IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "init-zero", sourceId = IdRange(0, 1))))))
lazy val module = new InitZeroModuleImp(this)
}

23
generators/chipyard/src/main/scala/example/NodeTypes.scala
View File

@@ -3,7 +3,6 @@ package chipyard.example
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import testchipip.TLHelper
// These modules are not meant to be synthesized.
// They are used as examples in the documentation and are only here
@@ -11,11 +10,11 @@ import testchipip.TLHelper
// DOC include start: MyClient
class MyClient(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode(TLMasterParameters.v1(
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "my-client",
sourceId = IdRange(0, 4),
requestFifo = true,
visibility = Seq(AddressSet(0x10000, 0xffff))))
visibility = Seq(AddressSet(0x10000, 0xffff)))))))
lazy val module = new LazyModuleImp(this) {
val (tl, edge) = node.out(0)
@@ -29,7 +28,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
class MyManager(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
val beatBytes = 8
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x20000, 0xfff)),
resources = device.reg,
regionType = RegionType.UNCACHED,
@@ -40,7 +39,7 @@ class MyManager(implicit p: Parameters) extends LazyModule {
supportsPutFull = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsHint = TransferSizes(1, beatBytes),
fifoId = Some(0)))
fifoId = Some(0))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
val (tl, edge) = node.in(0)
@@ -50,7 +49,8 @@ class MyManager(implicit p: Parameters) extends LazyModule {
// DOC include start: MyClient1+MyClient2
class MyClient1(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
"my-client1", IdRange(0, 1))))))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -58,7 +58,8 @@ class MyClient1(implicit p: Parameters) extends LazyModule {
}
class MyClient2(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
"my-client2", IdRange(0, 1))))))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -83,8 +84,8 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
// DOC include start: MyManagerGroup
class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
address = Seq(AddressSet(0x0, 0xfff))))
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x0, 0xfff)))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -92,8 +93,8 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
}
class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
address = Seq(AddressSet(0x1000, 0xfff))))
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x1000, 0xfff)))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
// ...

2
generators/gemmini

Submodule generators/gemmini updated: b6389f3ea7...9e478ecce9

2
generators/icenet

Submodule generators/icenet updated: fb23840eab...90d52a6a84

2
project/build.properties
View File

@@ -1 +1 @@
sbt.version=1.5.5
sbt.version=1.8.2

2
scripts/build-setup.sh
View File

@@ -91,7 +91,7 @@ run_step() {
# Check for this, since many users will be attempting to use this with gemmini
if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
while true; do
read -p "WARNING: You are trying to install the esp-tools toolchain."$'n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
case "$validate" in
y | Y)
echo "Installing esp-tools."

1
scripts/init-submodules-no-riscv-tools-nolog.sh
View File

@@ -150,6 +150,5 @@ fi
cat << EOT >> env.sh
# line auto-generated by init-submodules-no-riscv-tools.sh
__DIR="$RDIR"
PATH=\$__DIR/bin:\$PATH
PATH=\$__DIR/software/firemarshal:\$PATH
EOT

14
scripts/init-vlsi.sh
View File

@@ -4,15 +4,25 @@
set -e
set -o pipefail
# Initialize HAMMER and CAD-plugins
git submodule update --init --recursive vlsi/hammer
# exit script if not in Chipyard conda env
if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
echo 'ERROR: Chipyard conda env not activated. Please source env.sh and run this script again.'
exit
fi
# Initialize HAMMER CAD-plugins
if [[ $1 != *openroad* ]] && [[ $2 != *openroad* ]]; then
git submodule update --init --recursive vlsi/hammer-cadence-plugins
pip install -e vlsi/hammer-cadence-plugins
git submodule update --init --recursive vlsi/hammer-synopsys-plugins
pip install -e vlsi/hammer-synopsys-plugins
git submodule update --init --recursive vlsi/hammer-mentor-plugins
pip install -e vlsi/hammer-mentor-plugins
fi
# Initialize HAMMER tech plugin
# And add tech plugin to conda dependencies
if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then
git submodule update --init --recursive vlsi/hammer-$1-plugin
pip install -e vlsi/hammer-$1-plugin
fi

82
scripts/split-bb-files.py Executable file
View File

@@ -0,0 +1,82 @@
#!/usr/bin/env python3
import json
import argparse
from collections import defaultdict
# Schema of *.f emitted by circt
"""
<gen-src-dir>/<long-name>/gen-collateral/SimUART.cc
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource_1.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink_1.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSource_2.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncQueueSink_2.sv
<gen-src-dir>/<long-name>/gen-collateral/AsyncResetSynchronizerShiftReg_w4_d3_i0.sv
"""
def bfs_collect_submodules(tree):
output = set()
q = [(tree['instance_name'], tree['module_name'], tree['instances'])]
while len(q) != 0:
front = q[0]
q.pop(0)
(inst, mod, child) = front
output.add(mod)
for c in child:
q.append((c['instance_name'], c['module_name'], c['instances']))
return output
def write_lines_to_file(lines, file_path):
with open(file_path, "w") as fp:
for line in lines:
fp.write("%s\n" % line)
if __name__ == "__main__":
parser = argparse.ArgumentParser(description='Create *.model.bb.f and *.top.bb.f blackbox filelists')
parser.add_argument('--in-bb-f', type=str, required=True, help='All blackbox files filelist (includes both MODEL/TOP files)')
parser.add_argument('--in-top-hrchy-json', type=str, required=True, help='List containing hierarchy of top modules (top-module-hierarchy.json)')
parser.add_argument('--in-anno-json', type=str, required=True, help='Anno. file with blackbox annotations')
parser.add_argument('--out-top-bb-f', type=str, required=True, help='List of blackbox files for TOP')
parser.add_argument('--out-model-bb-f', type=str, required=True, help='List of blackbox files for MODEL')
args = parser.parse_args()
# module_path -> list of bb paths (not fully resolved paths)
mod_bb_dict = defaultdict(list)
with open(args.in_anno_json, "r") as f:
anno_data = json.load(f)
for anno in anno_data:
if 'BlackBoxInlineAnno' in anno['class']:
mod_bb_dict[anno['target']].append(anno['name'])
if 'BlackBoxPathAnno' in anno['class']:
mod_bb_dict[anno['target']].append(anno['path'])
with open(args.in_top_hrchy_json) as ihj:
ihj_data = json.load(ihj)
top_inner_modules = bfs_collect_submodules(ihj_data)
with open(args.in_bb_f) as ibf:
lines = ibf.read().splitlines()
tbfs = set()
for mod_path, bb_files in mod_bb_dict.items():
leaf_mod = mod_path.split('.')[-1]
# if matched, add the fully resolved path to the top bb filelist
if leaf_mod in top_inner_modules:
for line in lines:
for bb_file in bb_files:
if bb_file in line:
tbfs.add(line)
# now tbfs should be complete (need to remove tbf files from original bb file for model bb)
mbfs = set()
for line in lines:
if not line in tbfs:
mbfs.add(line)
write_lines_to_file(tbfs, args.out_top_bb_f)
write_lines_to_file(mbfs, args.out_model_bb_f)

2
scripts/tutorial-patches/build.sbt.patch
View File

@@ -27,4 +27,4 @@ index ec36a85f..c0c2849a 100644
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)

34
scripts/upgrade-vlsi.sh Executable file
View File

@@ -0,0 +1,34 @@
#!/usr/bin/env bash
# exit script if any command fails
set -e
set -o pipefail
# exit script if not in Chipyard conda env
if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
echo 'ERROR: Chipyard conda env not activated. Please source env.sh and run this script again.'
exit
fi
# Get hammer submodules
package_names=$(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}')
package_list=(${package_names})
plen="${#package_list[@]}"
if [[ ${plen} -gt 0 ]]; then
for p in "${package_list[@]}"; do
cd ${p}
echo "Updating current directory: $PWD"
git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
git pull
cd - > /dev/null
git add ${p}
pip install -e ${p} --upgrade
done
fi
# Upgrade hammer-vlsi separately.
pip install hammer-vlsi --upgrade

5
sims/common-sim-flags.mk
View File

@@ -20,7 +20,7 @@ SIM_CXXFLAGS = \
-std=c++17 \
-I$(RISCV)/include \
-I$(dramsim_dir) \
-I$(OUT_DIR) \
-I$(GEN_COLLATERAL_DIR) \
$(EXTRA_SIM_CXXFLAGS)
SIM_LDFLAGS = \
@@ -33,6 +33,3 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

8
sims/vcs/Makefile
View File

@@ -38,13 +38,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR)
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
$(foreach file,\
$^,\
$(SIM_FILE_REQS),\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables

14
sims/verilator/Makefile
View File

@@ -66,13 +66,13 @@ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
# copy files and add -FI for *.h files in *.f
$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR)
cp -f $^ $(OUT_DIR)
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
$(foreach file,\
$^,\
$(SIM_FILE_REQS),\
$(if $(filter %.h,$(file)),\
echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\
echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
echo "-FI $(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;,\
echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables
@@ -143,7 +143,7 @@ CHIPYARD_VERILATOR_FLAGS := \
# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
# NOTE: defer the evaluation of this until it is used!
PLATFORM_OPTS = $(shell \
if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \
if grep -qiP "module\s+(CVA6|NVDLA)" $(GEN_COLLATERAL_DIR)/*.*v; \
then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
@@ -181,7 +181,7 @@ VERILATOR_CXXFLAGS = \
-DTEST_HARNESS=V$(VLOG_MODEL) \
-DVERILATOR \
-include $(build_dir)/$(long_name).plusArgs \
-include $(OUT_DIR)/verilator.h
-include $(GEN_COLLATERAL_DIR)/verilator.h
VERILATOR_LDFLAGS = $(SIM_LDFLAGS)

2
toolchains/riscv-tools/riscv-isa-sim

Submodule toolchains/riscv-tools/riscv-isa-sim updated: 461767199a...e7d6aff19a

2
tools/barstools

Submodule tools/barstools updated: b71c31e66e...9760528f1d

31
variables.mk
View File

@@ -67,7 +67,7 @@ SUB_PROJECT ?= chipyard
ifeq ($(SUB_PROJECT),chipyard)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= $(SBT_PROJECT)
CONFIG ?= RocketConfig
CONFIG_PACKAGE ?= $(SBT_PROJECT)
@@ -79,7 +79,7 @@ endif
ifeq ($(SUB_PROJECT),hwacha)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= freechips.rocketchip.system
CONFIG ?= HwachaConfig
CONFIG_PACKAGE ?= hwacha
@@ -91,7 +91,7 @@ endif
ifeq ($(SUB_PROJECT),testchipip)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= chipyard.unittest
CONFIG ?= TestChipUnitTestConfig
CONFIG_PACKAGE ?= testchipip
@@ -103,7 +103,7 @@ endif
ifeq ($(SUB_PROJECT),icenet)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= chipyard.unittest
CONFIG ?= IceNetUnitTestConfig
CONFIG_PACKAGE ?= icenet
@@ -115,7 +115,7 @@ endif
ifeq ($(SUB_PROJECT),constellation)
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= constellation.test
CONFIG ?= TestConfig00
CONFIG_PACKAGE ?= constellation.test
@@ -161,18 +161,18 @@ MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json
MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json
MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
# hardcoded firtool outputs
MFC_FILELIST = $(OUT_DIR)/filelist.f
MFC_BB_MODS_FILELIST = $(OUT_DIR)/firrtl_black_box_resource_files.f
MFC_TOP_SMEMS_JSON = $(OUT_DIR)/metadata/seq_mems.json
MFC_MODEL_SMEMS_JSON = $(OUT_DIR)/metadata/tb_seq_mems.json
MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f
MFC_BB_MODS_FILELIST = $(GEN_COLLATERAL_DIR)/firrtl_black_box_resource_files.f
MFC_TOP_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/seq_mems.json
MFC_MODEL_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/tb_seq_mems.json
# macrocompiler smems in/output
SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf
TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v
TOP_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).top.mems.v
TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir
MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf
MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v
MODEL_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).model.mems.v
MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir
# top module files to include
@@ -182,6 +182,10 @@ MODEL_MODS_FILELIST ?= $(build_dir)/$(long_name).model.f
# list of all blackbox files (may be included in the top/model.f files)
# this has the build_dir appended
BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f
# top blackbox module files to include
TOP_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).top.bb.f
# model blackbox module files to include (not including top blackbox modules)
MODEL_BB_MODS_FILELIST ?= $(build_dir)/$(long_name).model.bb.f
# all module files to include (top, model, bb included)
ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f
@@ -198,7 +202,8 @@ sim_common_files ?= $(build_dir)/sim_files.common.f
# java arguments used in sbt
#########################################################################################
JAVA_HEAP_SIZE ?= 8G
export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(base_dir)/.java_tmp
JAVA_TMP_DIR ?= $(base_dir)/.java_tmp
export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR)
#########################################################################################
# default sbt launch command
@@ -254,7 +259,7 @@ gen_dir=$(sim_dir)/generated-src
# per-project output directory
build_dir=$(gen_dir)/$(long_name)
# final generated collateral per-project
OUT_DIR ?= $(build_dir)/gen-collateral
GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral
#########################################################################################
# assembly/benchmark variables

2
vcs.mk
View File

@@ -51,7 +51,7 @@ VCS_NONCC_OPTS = \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \
+incdir+$(OUT_DIR)
+incdir+$(GEN_COLLATERAL_DIR)
PREPROC_DEFINES = \
+define+VCS \

190
vlsi/Makefile
View File

@@ -21,8 +21,9 @@ include $(base_dir)/variables.mk
sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?= asap7
tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
$(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
$(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
$(shell python3 -c "import os, hammer.technology.$(tech_name);\
print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
$(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/$(tech_name))
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
@@ -34,15 +35,14 @@ else
endif
ENV_YML ?= $(vlsi_dir)/env.yml
TECH_CONF ?= $(if $(filter $(tech_name),asap7), example-asap7.yml,\
example-sky130.yml)
TECH_CONF ?= example-$(tech_name).yml
TOOLS_CONF ?= example-tools.yml
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF)
HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
./example-vlsi-sky130,\
./example-vlsi)
VLSI_TOP ?= $(TOP)
VLSI_HARNESS_DUT_NAME ?= chiptop
VLSI_MODEL_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),)
@@ -54,28 +54,36 @@ endif
#########################################################################################
# general rules
#########################################################################################
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
extra_v_includes = $(build_dir)/EICG_wrapper.v
ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB = /dev/null
else
VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
VLSI_BB = $(sim_top_blackboxes)
endif
.PHONY: default verilog
.PHONY: default all
default: all
all: drc lvs
verilog: $(ALL_RTL)
#########################################################################################
# import other necessary rules and variables
#########################################################################################
include $(base_dir)/common.mk
#########################################################################################
# process RTL
#########################################################################################
VLSI_RTL = $(build_dir)/syn.f
ifneq ($(CUSTOM_VLOG), )
RTL_DEPS = $(CUSTOM_VLOG)
else
RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE)
endif
$(VLSI_RTL): $(RTL_DEPS)
ifneq ($(CUSTOM_VLOG), )
> $(VLSI_RTL)
$(foreach file,$^,echo $(file) >> $(VLSI_RTL))
else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
endif
#########################################################################################
# srams
#########################################################################################
@@ -99,121 +107,6 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
cd $(vlsi_dir) && cp output.json $@
#########################################################################################
# simulation input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
include $(vlsi_dir)/sim.mk
$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@
for x in $(VCS_NONCC_OPTS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " options_meta: 'append'" >> $@
echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif
$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@
POWER_CONF = $(OBJ_DIR)/power-inputs.yml
include $(vlsi_dir)/power.mk
$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@
endif
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
#########################################################################################
# synthesis input configuration
#########################################################################################
@@ -223,21 +116,36 @@ ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(SRAM_CONF)
endif
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
$(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " input_files:" >> $@
for x in $(VLSI_RTL); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@
for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
for x in $$(cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
#########################################################################################
# simulation and power input configuration
#########################################################################################
include $(base_dir)/vcs.mk
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(build_dir)
cp -f $(SIM_FILE_REQS) $(build_dir)
$(foreach file,\
$(SIM_FILE_REQS),\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
include $(vlsi_dir)/sim.mk
include $(vlsi_dir)/power.mk
#########################################################################################
# AUTO BUILD FLOW
#########################################################################################

7
vlsi/example-asap7.yml
View File

@@ -1,6 +1,6 @@
# Technology Setup
# Technology used is ASAP7
vlsi.core.technology: asap7
vlsi.core.technology: "hammer.technology.asap7"
# Specify dir with ASAP7 Calibre deck tarball
technology.asap7.tarball_dir: "/path/to/asap7"
# Specify PDK and std cell install directories
@@ -94,7 +94,4 @@ vlsi.inputs.pin.assignments: [
]
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
vlsi.core.sram_generator_tool_path_meta: "append"
vlsi.core.sram_generator_tool: "hammer.technology.asap7.sram_compiler"

30
vlsi/example-openroad.yml
View File

@@ -1,22 +1,10 @@
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
# Yosys options
vlsi.core.synthesis_tool: "yosys"
vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
# Innovus options
vlsi.core.par_tool: "openroad"
vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"]
vlsi.core.par_tool_path_meta: "append"
# Magic options
vlsi.core.drc_tool: "magic"
vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"]
drc.magic.magic_bin: "magic"
# Netgen options
vlsi.core.lvs_tool: "netgen"
vlsi.core.lvs_tool_path: ["hammer/src/hammer-vlsi/lvs"]
vlsi.core.build_system: make
# Yosys
vlsi.core.synthesis_tool: "hammer.synthesis.yosys"
# OpenROAD
vlsi.core.par_tool: "hammer.par.openroad"
# Magic
vlsi.core.drc_tool: "hammer.drc.magic"
# Netgen
vlsi.core.lvs_tool: "hammer.lvs.netgen"

7
vlsi/example-sky130.yml
View File

@@ -1,6 +1,6 @@
# Technology Setup
# Technology used is Sky130
vlsi.core.technology: sky130
vlsi.core.technology: "hammer.technology.sky130"
vlsi.core.max_threads: 12
@@ -71,7 +71,4 @@ vlsi.inputs.pin.assignments: [
]
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"]
vlsi.core.sram_generator_tool_path_meta: "append"
vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

4
vlsi/example-tech.yml
View File

@@ -1,7 +1,5 @@
# Technology Setup
vlsi.core.technology: <tech_name>
vlsi.core.technology_path: ["hammer-<tech_name>-plugin"]
vlsi.core.technology_path_meta: append
vlsi.core.technology: "hammer.technology.<tech_name>"
# technology files installation directory
technology.<tech_name>.install_dir: "</path/to/technology/pdk/>"

41
vlsi/example-tools.yml
View File

@@ -1,36 +1,23 @@
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
# You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: []
vlsi.core.sram_generator_tool_path_meta: "append"
# Tool options. Replace with your tool plugin of choice.
vlsi.core.build_system: make
# Genus options
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "1813"
vlsi.core.synthesis_tool: "hammer.synthesis.genus"
synthesis.genus.version: "211"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "191_ISR3"
vlsi.core.par_tool: "hammer.par.innovus"
par.innovus.version: "211"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options
vlsi.core.drc_tool: "calibre"
vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
drc.calibre.version: "2017.3_38.30"
vlsi.core.lvs_tool: "calibre"
vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
lvs.calibre.version: "2017.3_38.30"
vlsi.core.drc_tool: "hammer.drc.calibre"
drc.calibre.version: "2022.2_24.16"
vlsi.core.lvs_tool: "hammer.lvs.calibre"
lvs.calibre.version: "2022.2_24.16"
# VCS options
vlsi.core.sim_tool: "vcs"
vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
sim.vcs.version: "P-2019.06-SP2-5"
vlsi.core.sim_tool: "hammer.sim.vcs"
sim.vcs.version: "S-2021.09-SP1-1"
# Voltus options
vlsi.core.power_tool: "voltus"
vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
vlsi.core.power_tool_path_meta: "append"
power.voltus.version: "191_ISR3"
vlsi.core.power_tool: "hammer.power.voltus"
power.joules.version: "211"
power.voltus.version: "211_ISR3"
# NOTE (about VCS+Voltus versions): if using FSDB, the VCS version should be approx 2 years older than the Voltus version for compatibility

17
vlsi/example-vlsi
View File

@@ -5,12 +5,11 @@
import os
import hammer_vlsi
from hammer_vlsi import CLIDriver, HammerToolHookAction
from hammer.vlsi import CLIDriver, HammerTool, HammerToolHookAction
from typing import Dict, Callable, Optional, List
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
def example_place_tap_cells(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -18,7 +17,7 @@ def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
def example_add_fillers(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -26,7 +25,7 @@ def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
def example_tool_settings(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
@@ -43,16 +42,16 @@ class ExampleDriver(CLIDriver):
# make_pre_insertion_hook will execute the custom hook before the specified step
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# make_post_insertion_hook will execute the custom hook after the specified step
# hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
]

19
vlsi/example-vlsi-sky130
View File

@@ -4,14 +4,13 @@
import os
import hammer_vlsi
from hammer_vlsi import CLIDriver, HammerToolHookAction
from hammer.vlsi import CLIDriver, HammerTool, HammerToolHookAction
from typing import Dict, Callable, Optional, List
from technology.sky130 import SKY130Tech
from hammer.technology.sky130 import SKY130Tech
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
def example_place_tap_cells(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -19,7 +18,7 @@ def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
def example_add_fillers(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -27,7 +26,7 @@ def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
def example_tool_settings(x: HammerTool) -> bool:
if x.get_setting("vlsi.core.technology") == "sky130":
x.append('''
# TODO
@@ -45,16 +44,16 @@ class ExampleDriver(CLIDriver):
# make_pre_insertion_hook will execute the custom hook before the specified step
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# make_post_insertion_hook will execute the custom hook after the specified step
# hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
]

1
vlsi/hammer

Submodule vlsi/hammer deleted from 41105f964f

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: 80f0e276cf...f9e323bd64

2
vlsi/hammer-mentor-plugins

Submodule vlsi/hammer-mentor-plugins updated: 67f57f1200...eca060af45

2
vlsi/hammer-synopsys-plugins

Submodule vlsi/hammer-synopsys-plugins updated: 7f9ae30eb4...e53fa5c51f

92
vlsi/power.mk
View File

@@ -1,10 +1,82 @@
.PHONY: $(POWER_CONF)
power-par: $(POWER_CONF) sim-par-debug
power-par-$(VLSI_TOP): $(POWER_CONF) sim-par-debug-$(VLSI_TOP)
power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
redo-power-par: $(POWER_CONF)
redo-power-par-$(VLSI_TOP): $(POWER_CONF)
redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
$(OBJ_DIR)/power-par-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)
POWER_CONF = $(OBJ_DIR)/power-inputs.yml
POWER_RTL_CONF = $(OBJ_DIR)/power-rtl-inputs.yml
POWER_SYN_CONF = $(OBJ_DIR)/power-syn-inputs.yml
POWER_PAR_CONF = $(OBJ_DIR)/power-par-inputs.yml
POWER_PAR_HIER_CONF = $(OBJ_DIR)/power-par-$(VLSI_TOP)-inputs.yml
.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF) $(POWER_PAR_HIER_CONF)
$(POWER_CONF): $(VLSI_RTL)
mkdir -p $(dir $@)
echo "power.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: TestDriver" >> $@
echo " tb_dut: 'testHarness/$(VLSI_MODEL_DUT_NAME)'" >> $@
ifneq ($(BINARY), )
echo " waveforms: [" >> $@
ifndef USE_VPD
echo " '$(sim_out_name).fsdb'" >> $@
else
echo " '$(sim_out_name).vpd'" >> $@
endif
echo " ]" >> $@
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
$(POWER_RTL_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.joules" > $@
echo "power.inputs:" >> $@
echo " level: rtl" >> $@
echo " input_files:" >> $@
for x in $$(cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \
done
$(POWER_SYN_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.joules" > $@
echo "power.inputs:" >> $@
echo " level: syn" >> $@
$(POWER_PAR_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.voltus" > $@
echo "power.inputs:" >> $@
echo " level: par" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
$(POWER_PAR_HIER_CONF): $(VLSI_RTL)
echo "vlsi.core.power_tool: hammer.power.voltus" > $@
echo "power.inputs:" >> $@
echo " level: par" >> $@
echo " database: '$(OBJ_DIR)/par-$(VLSI_TOP)/$(VLSI_TOP)_FINAL'" >> $@
power-rtl: $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug
power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug-$(VLSI_TOP)
power-rtl: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
power-rtl-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
redo-power-rtl: $(POWER_CONF) $(POWER_RTL_CONF)
redo-power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF)
redo-power-rtl: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
redo-power-rtl-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
power-syn: $(POWER_CONF) $(POWER_SYN_CONF) sim-syn-debug
power-syn-$(VLSI_TOP): $(POWER_CONF) $(POWER_SYN_CONF) sim-syn-debug-$(VLSI_TOP)
power-syn: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
power-syn-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
redo-power-syn: $(POWER_CONF) $(POWER_SYN_CONF)
redo-power-syn-$(VLSI_TOP): $(POWER_CONF) $(POWER_SYN_CONF)
redo-power-syn: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
redo-power-syn-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
power-par: $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug
power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF) sim-par-debug-$(VLSI_TOP)
power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
redo-power-par: $(POWER_CONF) $(POWER_PAR_CONF)
redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF)
redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
$(OBJ_DIR)/power-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)

78
vlsi/sim.mk
View File

@@ -1,4 +1,82 @@
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
$(SIM_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@
echo " tb_name: ''" >> $@ # don't specify -top
echo " input_files:" >> $@
for x in $$(cat $(sim_common_files)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@
for x in $(filter-out -f $(sim_common_files),$(VCS_NONCC_OPTS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " options_meta: 'append'" >> $@
echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \
done
echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@
endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(sim_common_files)
mkdir -p $(dir $@)
mkdir -p $(output_dir)
echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \
done
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif
$(SIM_TIMING_CONF): $(sim_common_files)
mkdir -p $(dir $@)
echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@
# Update hammer top-level sim targets to include our generated sim configs
redo-sim-rtl: $(SIM_CONF)
redo-sim-rtl-$(VLSI_TOP): $(SIM_CONF)

2
vlsi/tutorial.mk
View File

@@ -33,4 +33,6 @@ ifeq ($(tutorial),sky130-openroad)
EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-openroad
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_CUSTOM_FIRRTL_PASS = 1
endif