Commit Graph

142 Commits

Author SHA1 Message Date
abejgonzalez
a62c1f5010 Add a frag./config for MMIO only bridges 2023-03-09 20:09:46 -08:00
Jerry Zhao
9e7cdb6ccd Remove Ringbus config from firechip 2023-02-11 15:48:16 -08:00
Tushar Sondhi
95f30d0411 add more minimal firesim configs for testing (#1313) 2023-01-19 14:02:47 -08:00
tsondhi
ace6c7f490 add minimal firesim configs for testing fpga sims 2023-01-04 23:21:34 +00:00
Sagar Karandikar
8c56a5fe3c Merge pull request #1172 from ucb-bar/firesim-no-mem
firesim: Add a config with no mem port
2022-06-15 11:55:07 -07:00
David Biancolin
26dc18e878 firesim: Add a config with no mem port 2022-06-09 08:28:20 -07:00
Jerry Zhao
f8d83dddf5 Increase default SerialTL width to 32 (#1040) 2021-11-12 12:23:48 -08:00
Jerry Zhao
f668ffdb03 Switch PRCI to HarnessBinder/IOBinders 2021-09-29 11:39:52 -07:00
alonamid
610adfc3f7 address PR review comments 2021-06-03 22:23:17 -07:00
alonamid
f2b56072a1 remove crossings in single clock domain 2021-06-02 21:26:29 -07:00
alonamid
06b8cf84f9 update default firesim config freqs 2021-06-02 20:00:02 -07:00
alonamid
225cf9d29a update frequency config fragements 2021-06-01 16:40:31 -07:00
alonamid
b99d6bb7ac multiclock config multiple 2021-03-29 00:01:13 -07:00
alonamid
c93cd255ab sane firesim default target freqs 2021-03-25 23:28:07 -07:00
abejgonzalez
5ffad327db Bump testchipip 2021-03-21 15:34:01 -07:00
abejgonzalez
1e42113926 Splitting up FireSim default frequencies into a separate config frag. 2021-03-19 17:33:39 -07:00
abejgonzalez
6476c7e7f0 Small renaming/cleanup | Use LinkedHashMaps 2021-03-15 16:54:42 -07:00
Abraham Gonzalez
6ab8f8f8fc Update FireSim to support harness clocks | Small config renaming 2021-03-08 22:03:07 +00:00
Abraham Gonzalez
3d962180be Cleanup | Fix BlockDevice clocking issues 2021-03-03 19:44:55 +00:00
Abraham Gonzalez
c52fce79ae Fix FireChip compilation | Remove extra DefaultSerialTL in bridges 2021-03-03 07:25:49 +00:00
abejgonzalez
f850df7a9f General renaming / cleanup 2021-03-02 22:58:05 -08:00
Abraham Gonzalez
1d287bede5 Enlarge serial width | Bugfix loadmem disable | Add TracerV 2021-03-03 02:43:38 +00:00
Abraham Gonzalez
a3e22c78de First attempt at getting Offchip AXI port 2021-02-28 22:27:18 +00:00
Albert Magyar
f7a98f23bc Merge pull request #756 from ucb-bar/16-largeboom
Add 16-core LargeBOOM config to firechip
2021-01-13 15:36:51 -08:00
Albert Magyar
c481dc2ee8 Add 16-core LargeBOOM config to firechip
* Fix Jerry's comment on accidentally mixing multiple BOOM configs
2021-01-12 23:12:10 -08:00
David Biancolin
230bd81e0e [firechip] Update legacy firechip config 2020-11-09 09:26:30 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
David Biancolin
1b94e7f10c Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing 2020-10-16 23:21:20 +00:00
Alon Amid
2c935b4ad7 pull firesim mem model config into firesim tweaks 2020-10-15 17:07:51 +00:00
David Biancolin
9c8d2948af [firechip] Fix a broken config 2020-10-14 15:33:32 -07:00
David Biancolin
211c33f996 Address comments in #690 2020-10-14 14:42:45 -07:00
David Biancolin
986b5831c8 [clocking] Sketch out a topology that puts the MBUS is a separate domain 2020-10-09 07:23:17 -07:00
David Biancolin
b76972d34b Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux 2020-09-25 11:02:51 -07:00
David Biancolin
7b8a954d04 [firechip] Rework FireSim clocking to be more similar to default CY targets 2020-09-24 23:32:07 -07:00
Jerry Zhao
0d8e87126c Deprecate support for on-chip SerialAdapter 2020-09-14 19:43:32 -07:00
Jerry Zhao
6c5bce5430 Support Tilelink over serial 2020-09-13 11:59:16 -07:00
Jerry Zhao
a5385c0a54 Update testchipip/icenet to use rocket-chip Located API 2020-09-11 00:02:07 -07:00
Jerry Zhao
3258fd8db8 Remove JTAG from firesim comfigs due to @(posedge ~clk) issue 2020-09-03 23:53:51 -07:00
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
fdfef878af Merge branch 'dev' into diplomatic-clocks 2020-07-21 11:21:51 -07:00
David Biancolin
d5a2d43f85 Merge pull request #612 from ucb-bar/zynq-target
[firechip] Add a small target that should fit on all hosts
2020-07-10 18:12:34 -07:00
Albert Ou
b55e579c91 Override default baud rate for FireChip
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
2020-07-07 23:00:14 -07:00
Jerry Zhao
56e1aeb400 Support FireSim diplomatic multiclock 2020-07-07 20:54:31 -07:00
David Biancolin
1dd3ea4aeb Update TargetConfigs.scala 2020-06-27 13:44:52 -07:00
David Biancolin
486cc5fce1 [firechip] Add a small target that should fit on all hosts 2020-06-20 13:57:11 -07:00
Jerry Zhao
d245df9133 Bump Rocketchip to June 2020 for Tile changes 2020-06-18 17:25:31 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00