wu-arch/chipyard
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56 Commits

Author SHA1 Message Date
Abraham Gonzalez
d0bec3fba7 Ariane Integration (#448) 
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile

* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore

* [firesim] bump

* [ci] add midas ariane tests

* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments

* [ci] remove references to local verilator install

* [verilator] update flags

* [verilator] minimal set of flags for ariane

* [ariane] bump ariane to master

* [ci] revert to 4.016 verilator

* [ci] install verilator to ci server | misc compile fixes

* [ci/make] add longer ci timeout | update when assert is added in verilator sim

* [firesim] bump for misc. updates

* [make/ci] cleanup makefile and remove firesim tests of it

* [docs/firesim] bump and clean docs

* [firesim] bump

* [ci] use remote verilator for midas tests

* [misc] cleanup built.sbt more

* [firesim] bump

* [misc] bump build.sbt patch for tutorials

* [firesim/ci] cleanup and bump firesim
 2020-03-09 18:06:41 -07:00
Jerry Zhao
ebfa545344 Generator unification 2020-02-13 12:33:28 -08:00
Jerry Zhao
49dbe8daba Rename top-level example package to chipyard 
* FireChip now directly uses the Chipyard Top
 2020-02-13 12:33:04 -08:00
Colin Schmidt
86a473dbf6 Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358) 
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
 2019-12-12 13:39:09 -08:00
Abraham Gonzalez
98ded4d7c0 Merge pull request #221 from ucb-bar/comment-sim-files 
Comment sim_* make variables
 2019-09-02 19:36:19 -07:00
Howard Mao
ab888d32a7 Merge pull request #215 from ucb-bar/dev-tracegen 
Add TraceGen project
 2019-08-31 05:21:51 +08:00
Howard Mao
d4c12f2b86 Merge pull request #211 from ucb-bar/clean_configs 
Cleanup configs | take ownership of Heterogeneous subsystem | improve verilator compile time
 2019-08-31 05:00:29 +08:00
Howard Mao
6a3212c6d7 add tracegen project 2019-08-30 11:38:07 -07:00
abejgonzalez
c9c166f4a6 comment on the sim_* variables 2019-08-30 01:27:14 -07:00
Jerry Zhao
e7c727372f Cleanup configs 2019-08-26 14:32:08 -07:00
Colin Schmidt
950aee0749 Change spaces to underscores in sim_out_name 
This fixes #209
 2019-08-26 12:38:21 -07:00
Colin Schmidt
aaa3b78965 Add jvm heap size parameter (#201) 2019-08-15 17:28:04 -07:00
abejgonzalez
a8dbc391a1 remove boom variables | update ci 2019-07-24 22:55:00 -07:00
abejgonzalez
89b312a889 move boom integration to chipyard 2019-07-24 22:42:21 -07:00
abejgonzalez
52f959f457 remove duplicate line 2019-07-16 18:57:57 -07:00
abejgonzalez
b0b4078801 rename files | only remove .h on blackbox files 2019-07-16 18:55:44 -07:00
abejgonzalez
829687b254 move file name to variables.mk 2019-07-16 11:37:36 -07:00
Colin Schmidt
26a67fdbad Add verbose to debug runs (#148) 
* Add verbose to debug runs

* Reorg simulator flags for consistency, extensibility, and ease of use
 2019-07-15 22:15:57 -07:00
abejgonzalez
c44b6b721f fix variables for new boom naming 2019-07-01 11:57:29 -07:00
David Biancolin
473bc0aa4e Comment out FireChip make variables for now 2019-06-28 23:54:08 +00:00
David Biancolin
1bd9b08717 Merge branch 'rebar-dev' of https://github.com/ucb-bar/project-template into firesim-integration 2019-06-28 18:10:19 +00:00
David Biancolin
8700ff05e5 Merge remote-tracking branch 'origin/master' into firesim-integration 2019-06-28 04:53:18 +00:00
abejgonzalez
b556bee0b9 rename to "Chipyard" 2019-06-23 22:47:23 -07:00
abejgonzalez
4a667c3df9 correct naming in defaults 2019-06-12 14:54:49 -07:00
David Biancolin
f4fb0c42b1 Fix a number of build.sbt related problems 2019-05-29 22:26:04 +00:00
Abraham Gonzalez
c5c446f83b Merge pull request #93 from ucb-bar/rebar-dev-default-sim-flags 
Run Binary Default Flag Change
 2019-05-28 11:25:04 -07:00
abejgonzalez
ee62fa8bac renamed classes to BoomRocket to clarify | clearer comments | readd the bmark timeout 2019-05-27 17:21:19 -07:00
David Biancolin
c0d4e848ba WIP 2019-05-27 22:53:05 +00:00
abejgonzalez
c19855bfa6 shared heter-subsystem | single example SUB_PROJECT 2019-05-26 15:46:19 -07:00
abejgonzalez
c341ffe57d remove verbose for default 2019-05-24 21:22:46 -07:00
abejgonzalez
4af9ea9846 make default flags include timeout | all sims share flags 2019-05-24 09:47:50 -07:00
abejgonzalez
f071b522b2 ci harness fix for boomexample 2019-05-23 22:01:50 -07:00
abejgonzalez
838a34be51 move subsystem to boom | misc cleanup | bump boom 2019-05-23 21:47:35 -07:00
abejgonzalez
8b3fef85ce first attempt at heter. port 2019-05-23 15:47:52 -07:00
Jerry Zhao
bc54b24b85 Merge pull request #84 from ucb-bar/rebar-rc-may 
[WIP] Bump to May rocketchip | Support for large memory spaces
 2019-05-22 11:04:01 -07:00
abejgonzalez
30d54a6851 readme addition | pipe out output | renamed output files 2019-05-20 17:12:22 -07:00
abejgonzalez
65d6a900c3 rename output | helper rules to run binaries 2019-05-20 16:15:08 -07:00
Jerry Zhao
a7a4dd345b Bump to May rocketchip | Support for BigInt mems 2019-05-17 18:21:20 -07:00
abejgonzalez
deccae4959 hwacha depends on esp-tools | support java args 2019-05-13 17:17:32 -07:00
Jerry Zhao
cf9ef97676 Fix verilator clean 2019-05-07 23:05:13 -07:00
Jerry Zhao
fa0cc26737 Remove references to VCS in variables.mk 2019-04-29 15:11:23 -07:00
Jerry Zhao
2e53de6f22 Allow default configs for sub projects | have separate build_dir based on long_name 2019-04-25 13:33:08 -07:00
abejgonzalez
4c3dc0889c update make variable names | change hwacha to use its own generator 2019-04-24 00:43:44 -07:00
abejgonzalez
017a3c2350 support rocketchip longname from generator | extra comments | subprojects specify configs 2019-04-23 18:34:42 -07:00
Jerry Zhao
e0d1ba285d Add Hwacha config to example project 2019-04-23 16:20:23 -07:00
abejgonzalez
862c217ff4 allow rocket builds | asm tests pass 2019-04-23 11:50:36 -07:00
abejgonzalez
2bd70937cb support verilator | rename build variable 2019-04-22 23:26:13 -07:00
abejgonzalez
0e5e1bac15 fix test harness builds 2019-04-22 22:36:04 -07:00
abejgonzalez
eda0b113c1 more default subprojects | fix example builds 2019-04-21 14:41:02 -07:00
abejgonzalez
7faaa56f34 revert condDependsOn | put new firrtl jar into rocket 2019-04-18 11:39:19 -07:00