Commit Graph

259 Commits

Author SHA1 Message Date
Paul Rigge
cdcaf5c574 Missed an include end 2020-05-26 22:29:50 -07:00
Paul Rigge
312700e9da Fix some doc references 2020-05-26 18:24:46 -07:00
Paul Rigge
e6984e412b Use Chain for dsptools example.
Rename examples, bump dsptools to master, and incorporate feedback.
2020-05-26 23:00:37 +00:00
Paul Rigge
a6e96b6496 Update generators/chipyard/src/main/scala/DigitalTop.scala
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
2020-05-25 17:19:56 -07:00
Paul Rigge
7a0d8ea772 Update generators/chipyard/src/main/scala/DigitalTop.scala
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
2020-05-25 17:19:48 -07:00
Paul Rigge
77a624f488 Fix bad capitalization in doc reference 2020-05-25 14:19:52 -07:00
Paul Rigge
0cdc8fe244 Remove comments for non-unique portions of config fragment 2020-05-25 14:13:15 -07:00
Paul Rigge
ae1aa31fce Incorporate feedback 2020-05-25 20:23:19 +00:00
Paul Rigge
f56e367d59 Merge remote-tracking branch 'origin/dev' into HEAD 2020-05-23 22:49:51 +00:00
David Biancolin
dcf92ae15b Merge remote-tracking branch 'origin/dev' into generator-unification-p1 2020-05-19 18:53:08 +00:00
David Biancolin
fa2d620fb2 Remove commented code in ScalaTests 2020-05-19 00:50:14 +00:00
abejgonzalez
465e96a5ca bump testchipip 2020-05-18 12:21:17 -07:00
David Biancolin
96e838c773 [firechip] Set the cover property library in FireSim Harnesses 2020-05-17 00:18:54 +00:00
David Biancolin
99846c1ccb [firechip] Use the standard Chipyard generator 2020-05-17 00:18:17 +00:00
abejgonzalez
e913ddbbbe [traceio] bump testchipip 2020-05-16 16:45:50 -07:00
David Biancolin
8d5927913f [stage] Support using Chipyard's stage for non-processor designs 2020-05-16 22:49:06 +00:00
David Biancolin
73f8ec5017 [stage] Make config concatenation actually work 2020-05-16 22:49:06 +00:00
abejgonzalez
9dda27f20c [traceio] wdata: use option instead of 1.B wire 2020-05-16 14:47:15 -07:00
abejgonzalez
ca3c557fe2 [dromajo] change dromajo url | small cleanup 2020-05-16 13:43:14 -07:00
abejgonzalez
33e83e0644 [dromajo] separate documentation | move header file gen to tcip 2020-05-16 13:08:57 -07:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505)
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
2020-05-16 00:21:24 -07:00
John Wright
7c7b336c3f Add SPI flash support (#546)
* Add SPI flash configs, IOBinders, CI tests, and docs

* Add writable SPI flash support

* bump

* Fix CI

* Fix CI

* Update docs/Generators/TestChipIP.rst

Co-authored-by: Chick Markley <chick@qrhino.com>

* Maybe actually fix CI

* Fix broken merge

* Fix the tutorial patch

* bump tcip to master

* fix GPIO naming bug

Co-authored-by: Chick Markley <chick@qrhino.com>
2020-05-14 19:19:50 -07:00
alonamid
f0389bbe66 bump boom and ariane to master with RC firrtl 1.3 2020-05-13 10:03:30 -07:00
alonamid
9e95082a8a bump testchipip with buffer arg 2020-05-13 00:10:23 -07:00
alonamid
933d033569 sifive cache bump to RC firrtl 1.3 2020-05-12 23:34:01 -07:00
David Biancolin
6950ad7cee Comment out Ariane from ScalaTests 2020-05-12 22:01:14 +00:00
Colin Schmidt
596925020f Connect debug clocks when debug is tied off 2020-05-07 11:24:17 -07:00
Colin Schmidt
3c18880064 Increase verilator reset length 2020-05-06 18:39:42 -07:00
Colin Schmidt
a255417513 Update stage to use Dependency instead of classof 2020-05-05 15:24:51 -07:00
Colin Schmidt
43f6083b69 Many changes to begin the compilation with RC-1.3
Cores now have an extra CoreParam, useSupervisor which was set to
the default false. Whether a core has supervisor mode is the union
of this and useVM which defaults true so not change was made by this
addition.

BusTopologies are now set with the Config system rather than a system
mixin and so all configs now include the config most similar to the
previous mixin
Testchipip was updated to be able to replace the systembus, in this
new config system, with a ring bus.

The L2 cache repo needed a similar update on how to find the buses.
It currently points to the ucb-bar fork

Treadle is bumped to its release branch
2020-05-05 15:14:24 -07:00
Jerry Zhao
63c46d89c1 Bump sifive-blocks 2020-05-05 13:58:01 -07:00
alonamid
9b94570648 bump rocket chisel (3.3) and firrtl (1.3) 2020-05-05 11:02:28 -07:00
John Wright
794509aba9 [ci skip] Scaladoc and comment fixes (#542) 2020-05-04 14:39:05 -07:00
Paul Rigge
0cc643bfdb Switch FIR from UInt -> FixedPoint 2020-04-30 10:51:32 -07:00
Jerry Zhao
24fada1d9c Add WithNoUART fragment (#536) 2020-04-29 01:24:25 -07:00
Howard Mao
8df43203a2 separate testchipip ClockUtilTests and TestChipUnitTests 2020-04-28 10:32:28 -07:00
Howard Mao
b813caf6fd get icenet and testchipip unit tests working 2020-04-28 10:32:28 -07:00
Abraham Gonzalez
e22ff880e2 [firesim] generate rocket-chip based artefacts (#534) 2020-04-27 20:27:36 -07:00
David Biancolin
b26ed91b73 [CI] Convert FireSim tests to use ScalaTest 2020-04-26 21:11:31 -07:00
Ryan Lund
35cba5dfae Dsptools examples (#457)
* Add c test files for DSPTools example

* Update tests Makefile to build DSPTools c tests

* Add DSPTools example configs to ConfigMixins and RocketConfigs

* Add dsptools and rocket-dsptools as dependancies for example

* Add Scala implementations of DSPTools test blocks

* Clean up GenericFIR scala

* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial

* Update documentation, will need reworking once FIR is characterized as fixed point

* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain

* Fix capitalization in docs (#419)

* Add c test files for DSPTools example

* Update tests Makefile to build DSPTools c tests

* Add DSPTools example configs to ConfigMixins and RocketConfigs

* Add dsptools and rocket-dsptools as dependancies for example

* Add Scala implementations of DSPTools test blocks

* Clean up GenericFIR scala

* Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial

* Update documentation, will need reworking once FIR is characterized as fixed point

* Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain

* Update docs/Customization/Dsptools-Blocks.rst

Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>

* Docummentation update for clarity and to explain how this can be applied to a generalized block

* Some refactoring to get dsptools working with these examples

* Oops, old files crept in

Co-authored-by: Ryan Lund <ryan.lund@bwrcrdsl-4.eecs.berkeley.edu>
Co-authored-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
Co-authored-by: Paul Rigge <rigge@berkeley.edu>
2020-04-20 10:33:03 -07:00
David Biancolin
b303cf6e81 Rocket Chip Stage/Phase Bump (#503)
[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
2020-04-18 17:54:27 +00:00
David Biancolin
d49c30560c Merge remote-tracking branch 'origin/dev' into diplomatic-bridges 2020-04-06 23:59:19 -07:00
David Biancolin
ba19987984 [firechip] Label FASED instances with an associated memory region name 2020-04-04 18:38:34 -07:00
John Wright
1f98c84210 Add ChipTop to enable real chip configs with IO cells, etc. (#480)
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
2020-04-01 14:03:56 -07:00
Abraham Gonzalez
3d253c0f67 [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder
2020-03-30 17:04:45 -07:00
David Biancolin
fe2f50f879 Merge pull request #468 from ucb-bar/firesim-multiclock
Target-Facing Support for Multiclock Simulation in FireSim
2020-03-25 10:41:58 -07:00
David Biancolin
fbc47af67c Bump testchipip to dev
[ci skip]
2020-03-25 10:20:22 -07:00
David Biancolin
1b7158835a Bump firesim for CI 2020-03-24 10:43:01 -07:00
Howard Mao
2528708c15 add documentation on ring network and system bus 2020-03-19 10:13:03 -07:00